Low power

Open Access Article

1 - Design of Low Power Single-Bit Full-Adder Cell Based on Pass-Transistor Logic
Mehdi Sayyaf Abdolrasool Ghasemi Roozbeh Hamzehyan

10.30495/jce.2022.692834

In today's electronic and digital world, increasing demand for portable systems has led the electronics industry and chip design technology to reduce power consumption methods, and therefore power consumption has become an important criterion in this field. Also, increa More

In today's electronic and digital world, increasing demand for portable systems has led the electronics industry and chip design technology to reduce power consumption methods, and therefore power consumption has become an important criterion in this field. Also, increasing the speed of chips and reducing the propagation delay of circuits has always been an important goal of digital design engineers. Since the Adder element is one of the important elements in many digital systems, so today various Adders with different technologies and design approaches have been proposed, each of which has certain advantages and disadvantages. This paper presents a low-power single-bit full-adder cell design that is based on pass-transistor logic.This circuit is used in the arithmetic logic units of digital signal processors and also in several electronic and digital communication systems that operate within the frequency range of in 1GHz. The proposed cell exploits the pass transistor techniques and XOR-XOR structures to improve the design parameters namely power consumption, propagation delay, power–delay product, and the number of transistors. The proposed circuit is designed using 180nm CMOS technology and the simulation results show that for a supply voltage of 1.8V, the power consumption, delay, and power–delay product have been achieved as 83 W, 89ps, and 7fJ respectively. Manuscript profile

Open Access Article

2 - Low Latency and Power Efficient Reversible Full Adder based on Toffoli Gates
Seyedeh Fatemeh Deymad Nabiollah Shiri Farshad Pesaran

10.30495/jce.2023.1988197.1207

The reversible circuits are useful in energy-saving applications because of their unique features. Hence, using 32 nm carbon nanotube field-effect transistor (CNTFET) technology and relying on Toffoli's reversible gates, a new full adder (FA) circuit is presented. The p More

The reversible circuits are useful in energy-saving applications because of their unique features. Hence, using 32 nm carbon nanotube field-effect transistor (CNTFET) technology and relying on Toffoli's reversible gates, a new full adder (FA) circuit is presented. The proposed circuit has 4 basic Toffoli gates and 18 transistors. 3 of the 4 gates have the same transistor schematic with a constant-ON transistor, but the remaining gate has only two transistors. The proposed circuit has 3 constant inputs and 4 garbage outputs. As a new method, in the proposed circuit, only one type of reversible gate is used. The results show the superiority of the proposed FA in terms of power consumption and energy dissipation. By implementing the proposed FA and other circuits in a 4-bit and 8-bit ripple carry adder (RCA), the proposed circuit shows improvements by 6.83% and 11.25% in terms of power and energy, respectively, compared to the main competitor. Also, in an 8-bit RCA, the proposed FA has a 2% saving compared to the nearest competitor and 27% compared to the worst circuit in terms of the power-delay-area-product (PDAP). These results show the designed FA as a favorable option for complex structures with high-order bits. Manuscript profile

Open Access Article

3 - Design of high linearity large dynamic-range delay-element for low-voltage low-power applications
آتنا Varzandeh Esfahani S. M Fahmideh Akbarian

Designing a high efficiency delay-element is a challenge for low-power low-voltage digital circuits. The delay element circuit has a considering effect on efficiency of low-voltage digital circuits. In sub-micron technologies that lowering the power and the voltage of t More

Designing a high efficiency delay-element is a challenge for low-power low-voltage digital circuits. The delay element circuit has a considering effect on efficiency of low-voltage digital circuits. In sub-micron technologies that lowering the power and the voltage of the systems is essentially required, design of a highly linear large dynamic range delay element is an important issue for designers. In this paper high linearity delay element is proposed employing the sub-threshold source coupled logic (STSCL) circuits. The presented circuit has a considerable controlling of the delay value by a control voltage. Improvements of dynamic-range and the linearity of the circuit show the operation of the delay element in sub-threshold region. Manuscript profile

Open Access Article

4 - Improved of Linearity Performance With low Common-mode Voltage Variations for Non-binary Successive Approximation ADC With a Monotonic Switching method
Nasrin Shayestehnezhad عبدالرسول Ghasemi

In this paper, a fully differential successive approximation A/D converter is presented using the extended non-binary search algorithm with an accuracy of 10-bits, 11 comparison steps, and the sampling rate of 4.17MS/s which is suitable for low-power applications becaus More

In this paper, a fully differential successive approximation A/D converter is presented using the extended non-binary search algorithm with an accuracy of 10-bits, 11 comparison steps, and the sampling rate of 4.17MS/s which is suitable for low-power applications because it does not require to be calibration. In the non-binary search algorithm, there are overlaps between the search rang, that allow comparison decision errors to be digitally corrected. To improve the linear behavior of the proposed structure, a capacitive array D/A converter with non-binary weight is implemented, and the sampling frequency is increased compared to the conventional successive approximation converter through proper selection of non-binary capacitances of the capacitive array. The proposed structure operates based on monotonic switching logic. This switching method reduces the power consumption of DAC compared to conventional switching. The proposed structure is designed using 180nm CMOS technology and the simulation results show that for a supply voltage of 1.8V, signal to noise and distortion ratio (SNDR) is 61.35dB, power consumption is 78.14µW, and figure of merit is 19.57(fj/Conv.step). Manuscript profile

Open Access Article

5 - Analysis and Design of a High Performance Radix-4 Booth Scheme in CMOS Technology
Ali Rahnamaei

10.52547/mjtd.10.2.67

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Open Access Article

6 - Decimal Convolutional Code and its Decoder for Low-Power applications
Ali Ghasemi khah Yosef Seifi Kavian

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7 - Improving the Performance of RPL Routing Protocol for Internet of Things
Zahra Aslani Hadi Sargolzaey

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Open Access Article

8 - The effect of low-power laser on the promotion of spermatogenesis in a mouse model of azoospermia (in-vivo)
habib tajalli Masoud Maleki Esmail Safavi Reza Shahi Fatemeh Firoozi Zahra Akbarpour Ali reza Sotoudeh Khyaban

10.30495/ijbbo.2022.1964975.1014

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Open Access Article

9 - A review on power reducing methods of neural recording amplifiers
samira mehdipour mehdi habibi

Implantable multi-channel neural recording Microsystems comprise a large number of neural amplifiers, that can affect the overall power consumption and chip area of the analog part of the system.power, noise, size and dc offset are the main challenge faced by designers. More

Implantable multi-channel neural recording Microsystems comprise a large number of neural amplifiers, that can affect the overall power consumption and chip area of the analog part of the system.power, noise, size and dc offset are the main challenge faced by designers. Ideally the output of the opamp should be at zero volts when the inputs are grounded.In reality the input terminals are at slightly different dc potentials.The input offset voltage is defined as the voltage that must be applied between the two input terminals of the opamp to obtain zero volts at the output. Amplifier must have capability to reject this dc offset. First method that uses a capacitor feedback network with ac coupling of input devices to reject the offset is very popular in designs.very small low-cutoff frequency.The second method employs a closed-loop resistive feedback and electrode capacitance to form a highpass filter.Moreover,The third method adopts the symmetric floating resistor the feedback path of low noise amplifier to achieve low-frequency cutoff and rejects DC offset voltage. .In some application we can use folded cascade topology.The telescopic topology is a good candidate in terms of providing large gain and phase margin while dissipating small power. the cortical VLSI neuron model reducing power consumption of circuits.Power distribution is the best way to reduce power, noise and silicon area. The total power consumption of the ampliﬁer array is reduced by applying the partial OTA sharing technique. The silicon area is reduced as a beneﬁt of sharing the bulky capacitor Manuscript profile

Open Access Article

10 - Design of Non-Uniform Sample and Hold Circuit for Biomedical Signal Processing Applications
Sara Bagher Nasrabadi Mehdi Dolatshahi Sayed Mohammad Ali Zanjani Hossein Poorghasem

By reducing the amount of data in bioprocessor circuits, the required memory and power consumption are reduced. Therefore, non-uniform sampling (NUS) is feasible, and a sample-and-hold circuit can be used to non-uniformly sample bio-signals and reduce the volume of the More

By reducing the amount of data in bioprocessor circuits, the required memory and power consumption are reduced. Therefore, non-uniform sampling (NUS) is feasible, and a sample-and-hold circuit can be used to non-uniformly sample bio-signals and reduce the volume of the data from vital signals. In the present study, a new closed-loop non-uniform sample-and-hold circuit along with a differential clock generator circuit is proposed. The proposed design consumes low power and can minimize the volume of the generated bio-signal data in the frequency range corresponding to vital signals. The proposed non-uniform clock generator circuit uses two comparators with PMOS and NMOS inputs and a control circuit with a few logic gates. After detecting the rate of heart signal variations, the proposed circuit generates non-uniform clock signals at two frequencies of 1000 and 100 Hz for fast and slow variations, respectively. The output signal of the sampling circuit is reconstructed by using resampling and interpolation in MATLAB. Simulations are performed in Cadence in 0.18 µm technology with a supply voltage of 1.8 V. The simulation results show a percentage root mean square difference (PRD) of 2.3%, a mean square error (MSE) of 8.57×10-5 and a signal-to-noise ratio (SNR) of 71 dB. These results indicate the proper performance of the proposed circuit in comparison with previous designs. Manuscript profile

Open Access Article

11 - Design and Simulation of a Bulk Driven Operational Transconductance Amplifier Based on CNTFET Technology
Sayed Mohammad Ali Zanjani Mostafa Parvizi

In this paper, a new two-stage OTA is proposed which meeting the needs of high gain, low power and low noise, and designed based on the gm/ID technique with bulk driven method. It is noteworthy that due to the limitations of CMOS technology, CNTFET technology used for t More

In this paper, a new two-stage OTA is proposed which meeting the needs of high gain, low power and low noise, and designed based on the gm/ID technique with bulk driven method. It is noteworthy that due to the limitations of CMOS technology, CNTFET technology used for the circuit designs. Moreover, to improve the linearity of the circuit, triode transistors used in both stages of amplifiers. The simulation results of the proposed OTA are performed under 1V of supply voltage and 1pF of load capacitors in the HSPICE tool. According to the simulation results, the proposed circuit consumes less than 27 µW of power and offers a high gain of 98 dB. The CMRR and PSRR values of the proposed circuit are 121 dB and 152 dB, respectively. The input referred noise is 0.92 nV/√Hz and the slew rate of the proposed circuit is 111 V/µs, which shown the better figure of merit (FOM) in compression with the previous works.   Manuscript profile

Open Access Article

12 - Design of a Low Power Temperature Sensor Based on Sub-Threshold Performance of Carbon Nanotube Transistors with an Inaccuracy of 1.5ºC for the range of -30 to 125ºC
Sayed Mohammad Ali Zanjani Masoumeh Aalipour Mostafa Parvizi

In this paper, a new temperature sensor based on the performance of carbon nanotube transistors in the subthreshold region is designed and simulated which leads to reduction of power consumption. Also, a differential amplifier is used in the output of the sensor. in ord More

In this paper, a new temperature sensor based on the performance of carbon nanotube transistors in the subthreshold region is designed and simulated which leads to reduction of power consumption. Also, a differential amplifier is used in the output of the sensor. in order to keep the values of gain and common mode level voltage due to temperature changes, a method has been proposed that can compensate for these parameters variation due to temperature variation in the range of -30 ºC to +125 ºC. The proposed temperature sensor with its amplifier can be used as a system on the chip surface for temperature monitoring and control. The proposed temperature sensor in the CNTFET carbon nanotube field effect transistor technology with a supply voltage of 0.5 V in the sub-threshold area is simulated by HSPICE software with a 32nm CNT model. The simulation results show that at proposed circuits can measure the temperature in range of -30 ºC to +125 ºC linearly with a sensitivity of 1 mV/ ºC and consumes only 123 nW at room temperature. Also, the error measured at 125 ºC is about 2.5 mV, which means an error of 1.25 ºC at this temperature. Manuscript profile

Open Access Article

13 - Design of 4 Transistors and 1 Memristor Hybrid Nonvolatile Memory Cell with Low Power, High Speed, and High Density
Arash Alijani Behzad Ebrahimi Massoud Dousti

Memristor is the fourth fundamental element after resistor, capacitor, and inductor. Memristor can become an essential element of SRAM and DRAM caches because of its zero power consumption in data storage and non-volatile state. It can effectively improve the efficiency More

Memristor is the fourth fundamental element after resistor, capacitor, and inductor. Memristor can become an essential element of SRAM and DRAM caches because of its zero power consumption in data storage and non-volatile state. It can effectively improve the efficiency, speed, and power consumption of circuits. In this paper, we propose a 4T1M memory cell reducing the cell area by maintaining the maximum properties of 6T1M. To simulate the proposed memory cell, the length of the memristors is 10 nm, and the resistance of their on and off states is selected as 1 kΩ and 200 kΩ, respectively. Also, the cell MOS transistors are simulated by the 32 nm HP CMOS PTM model. Simulations in H-Spice software, at 0.9 V power supply, have been conducted to compare the proposed cell characteristics with two conventional six-transistor (6T) and six-transistor one-memristor (6T1M) cells. The results show that using a memristor in a memory cell causes zero power consumption during data storage for a long time and reduces the occupied area by 36.7% compared to the 6T1M cell. The speed of writing “1” data on the proposed cell is only 30 ps, which shows a 3-fold improvement compared to the 6T1M cell, but no significant change is observed when writing “0” data. The static power of the proposed cell is 133 times less than that of a six-transistor cell, and its dynamic power is about the same as the 6T1M cell, but it consumes 60 times less energy than a six-transistor cell. Manuscript profile

Open Access Article

14 - A 0.5 V Operational Transconductance Amplifier Based on Dynamic Threshold-Voltage MOSFET and Floating Gate MOSFET Inverters in 180 nm CMOS Technology
Amir Baghi Rahin Vahid Baghi Rahin

This paper presents a fully differential operational transconductance amplifier (OTA) based on the dynamic threshold-voltage MOSFET and floating gate MOSFET (DT/FGMOS) inverter with a supply voltage of 0.5 V. The proposed inverter in the structure of this OTA is a combi More

This paper presents a fully differential operational transconductance amplifier (OTA) based on the dynamic threshold-voltage MOSFET and floating gate MOSFET (DT/FGMOS) inverter with a supply voltage of 0.5 V. The proposed inverter in the structure of this OTA is a combination of the dynamic threshold-voltage MOSFET (DTMOS) technique (for all PMOS transistors) and the floating gate MOSFET (FGMOS) (for all NMOS transistors) in n-well process. In this circuit, feedforward and feedback paths have been used to limit the common-mode gain. The first stage has feedforward paths to eliminate the common-mode and the second stage has the common-mode feedback to stabilize the common-mode output voltage on Vdd/2. Based on the post-layout simulation results, the proposed OTA showed a gain of 61 dB with a unity gain frequency (UGF) of 1.1 MHz under 13 pF load capacitors. With the studies performed by Monte Carlo analysis, it was found that the OTA based on the proposed inverter can perform well under process variations and device mismatches. The proposed circuit in 180 nm CMOS technology occupies an area of 0.182 mm2 from the chip. Its power consumption is 17 µW and it can be used in low voltage and low power applications including portable equipment. According to studies, the use of DTMOS and FGMOS techniques can lead to the effective reduction of the threshold voltage of transistors and the good performance of the proposed OTA at low voltage. Manuscript profile

Open Access Article

15 - Designing a New Gate-Diffusion Input in Quantum-Dot Cellular Automata Technology
Hamidreza Sadrarhamii Sayed Mohammadali Zanjani Mehdi Dolatshahi Behrang Barekatain

Quantum-dot cellular automata (QCA) is a modern technology, which has higher speed, lower power consumption, higher density, and lower complexity than conventional technologies, such as CMOS. Moreover, the gate diffusion input (GDI) technique has been successful in redu More

Quantum-dot cellular automata (QCA) is a modern technology, which has higher speed, lower power consumption, higher density, and lower complexity than conventional technologies, such as CMOS. Moreover, the gate diffusion input (GDI) technique has been successful in reducing complexity, area, and energy consumption in low-power circuit designs. In this technique, a wide range of complex logic functions can be implemented using only two transistors as the main block. In this study, a QCA-based GDI block is proposed using only 11 cells as a standard design unit that can be used to implement basic functions such as AND, OR, MUX, BUFFER, NOT and XOR in digital circuits. QCADesigner simulations of the functions in 18 nm technology indicate the superior performance of the proposed block with only one clock cycle delay in performing the operations. Moreover, the power consumption analysis of the designed circuits is performed using QCADesigner. The advantages of the proposed circuit compared to previous designs are 31% reduction in cell count, 50% smaller surface area, and 17% reduction in total energy loss. Manuscript profile

Open Access Article

16 - Ultra low voltage and low power 4-2 compressor using FinFET transistors
Amir Baghi Rahin Vahid Baghi Rahin

A compressor is basic building blocks of many arithmetic circuits. Design of smaller area, low power consumption and high speed compressor is always in demand. As the channel length approaches nanometer scale, the use of MOSFET as the basic device in compressor now has More

A compressor is basic building blocks of many arithmetic circuits. Design of smaller area, low power consumption and high speed compressor is always in demand. As the channel length approaches nanometer scale, the use of MOSFET as the basic device in compressor now has reaching its performance limits such as average power dissipation and speed. In this paper, a 1-bit full adder cell using FinFET transistor based on PTM 32nm process model with 0.6 V supply voltage for mobile applications is proposed. Then, the proposed full adder cell is used in the structure of compressor and performance of the proposed 4: 2 compressor is evaluated with the simulation results obtained from HSPICE. The main parameters of proposed compressor such as power compression, delay, power-delay product (PDP) and energy-delay product (EDP) were measured and its superior performance has been proved by various simulations. Also, in comparison of MOSFET based compressor, the number of transistors is decreased to 42. Manuscript profile

Open Access Article

17 - Design of Low-Power CMOS OTA Using Bulk-Drive Technique
Maryam Ghadiri Modarres

This paper presents the design of low power CMOS- OTA (operational transconductance amplifier) using bulk drive (BD) technique with broad band. This technique is used for design of low power circuits with broad band for high frequency users, for example communication sy More

This paper presents the design of low power CMOS- OTA (operational transconductance amplifier) using bulk drive (BD) technique with broad band. This technique is used for design of low power circuits with broad band for high frequency users, for example communication systems, mobile communication and communication forming of medical electronics. OTA is the base of amplifier .It is a fundamental building part of analog systems. Recently analog designer has been paid to low voltage (LV),low power (LP) integrated circuits. Many techniques are used for the design of LV LP circuits, the bulk driven offers principle this designs. This paper suggests a bulk driven OTA in standard CMOS processes and supply voltage 0.8 volt DC. It used of improved wilson current mirror. The simulation results have been carried out by the HSPICE simulator in 180 nm CMOS technology. The open loop gain is enhanced to 17.4dB at unity gain band with (UGB) of 26.1 MHZ with sufficient output swing. Power consumption of the OTA is in range of few hundreds of nanowatts (6%). Manuscript profile

Open Access Article