Low Latency and Power Efficient Reversible Full Adder based on Toffoli Gates

Seyedeh Fatemeh Deymad ¹ ( Department of Electrical Engineering, Shiraz Branch, Islamic Azad University, Shiraz Iran )
Nabiollah Shiri ² ( Islamic Azad University Shiraz Branch )
Farshad Pesaran ³ ( Islamic Azad University, Shiraz Branch )

Submited date : 2023-06-09 Accepted date : 2023-07-15

Keywords: ripple carry adder, High speed, Low power, Toffoli gate. reversible design, Full adder,

Abstract :

The reversible circuits are useful in energy-saving applications because of their unique features. Hence, using 32 nm carbon nanotube field-effect transistor (CNTFET) technology and relying on Toffoli's reversible gates, a new full adder (FA) circuit is presented. The proposed circuit has 4 basic Toffoli gates and 18 transistors. 3 of the 4 gates have the same transistor schematic with a constant-ON transistor, but the remaining gate has only two transistors. The proposed circuit has 3 constant inputs and 4 garbage outputs. As a new method, in the proposed circuit, only one type of reversible gate is used. The results show the superiority of the proposed FA in terms of power consumption and energy dissipation. By implementing the proposed FA and other circuits in a 4-bit and 8-bit ripple carry adder (RCA), the proposed circuit shows improvements by 6.83% and 11.25% in terms of power and energy, respectively, compared to the main competitor. Also, in an 8-bit RCA, the proposed FA has a 2% saving compared to the nearest competitor and 27% compared to the worst circuit in terms of the power-delay-area-product (PDAP). These results show the designed FA as a favorable option for complex structures with high-order bits.

References:


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