Analysis and Design of a High Performance Radix-4 Booth Scheme in CMOS Technology
Subject Areas : Majlesi Journal of Telecommunication Devices
1 - Department of Electrical Engineering, Ardabil Branch, Islamic Azad University, Ardabil, Iran.
Keywords:
Abstract :
[1] Adam Osborne, “An Introduction to Microcomputers, Volume 1: Basic Concepts (2nd ed.),” Berkeley, California: Osborne-McGraw Hill, 1980, ISBN 0-931988-34-9.
[2] Ross Basset, “When is a Microprocessor not a Microprocessor? The Industrial Construction of Semiconductor Innovation,” In Finn, Bernard, Exposing Electronics, Michigan State University Press, p. 121, 2003, ISBN 0-87013-658-5.
[3] Jeffrey Shallit, “A Very Brief History of Computer Science,” CS 134, University of Waterloo, summer of 1995.
[4] M. Rafiquzzaman, “Fundamentals of Digital Logic and Microcomputer Design,” John Wiley & Sons, pp 251, 2005, ISBN 9780471733492.
[5] D. Naresh and G. Babu Kande, “High Speed Signed multiplier for Digital Signal Processing Applications,” IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE), Vol. 8, Issue 2, pp. 57-61.
[6] Andrew D. Booth, “A signed binary multiplication technique,” The Quarterly Journal of Mechanics and Applied Mathematics, Volume IV, Pt. 2, 1951.
[7] C. S. Wallace, “A suggestion for a fast multiplier,” IEEE Trans. on Electronic Comp. EC-13(1): 14-17, 1964.
[8] L. Dadda, “Some schemes for parallel multipliers,” Alta Frequenza. 34: 349–356, 1965.
[9] Parhami, Behrooz, “Computer Arithmetic: Algorithms and Hardware Designs,” Oxford University Press, New York, 2000, ISBN 0-19-512583-5.
[10] Shiann-Rong Kuang, Jiun-Ping Wang, and Cang-Yuan Guo, “Modified Booth Multipliers With a Regular Partial Product Array,” IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 56, No. 5, pp. 404-408, 2009.
[11] Ravindra P. Rajput, M.N. Shanmukha Swamy, “High speed Modified Booth Encoder multiplier for signed and unsigned numbers,” 14th International Conference on Modelling and Simulation, pp. 649-654, 2012.
[12] A. Fathi, S. Azizian, R. Fathi, H.G. Tamar, “Low latency, glitch-free booth encoder-decoder for high speed multipliers,” IEICE Electronics Express, Vol. 9, No. 16, pp. 1335-1341, 2012.
[13] A. Fathi, S. Azizian, Kh. Hadidi, A. Khoei, “Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations,” IEICE transactions on electronics, Vol. 95, No. 4, pp. 706-709, 2012.
[14] Honglan Jiang, Jie Han, Fei Qiao, and Fabrizio Lombardi, “Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation,” IEEE Transactions on Computers, Vol. 65, No. 8, pp. 2638-2644, Aug 2016.
[15] Saurabh Katariya, and Manish Singhal, “A Hybrid 4-bit Radix-4 Low Power Booth Multiplier With High Performance,” IEEE International Conference on Recent Advances and Innovation in Engineering (ICRAIE -2016), Dec 23-25, 2016.
[16] A N Nagamani, R Nikhil, Manish Nagaraj, and Vinod Kumar Agrawal, “Reversible Radix-4 Booth Multiplier for DSP Applications,” International Conference on Signal Processing and Communications (SPCOM), 2016.
[17] Alberto A. Del Barrio, and Rom´an Hermida, “A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers,” IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.
[18] Weiqiang Liu, Liangyu Qian, Chenghua Wang, Honglan Jiang, Jie Han, and Fabrizio Lombardi, “Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing,” IEEE Transactions on Computers, Vol. 66, No. 8, pp. 1435-1441, 2017.
[19] Ali Rahnamaei, Gholamreza Zare Fatin, and Abdollah Eskandarian, “High speed Radix-4 Booth scheme in CNTFET technology for high performance parallel multipliers,” Int. J. Nano Dimens., Vol.10, No. 3, pp. 281-290, 2019.
[20] Amir Fathi, Sarkis Azizian, Khayrollah Hadidi, Abdollah Khoei and Amin Chegeni, “CMOS Implementation of a Fast 4-2 Compressor for Parallel Accumulations,” 2012 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1476-1479, May 2012.
[21] Amir Fathi, Behbood Mashoufi, and Sarkis Azizian, “Very fast, high-performance 5-2 and 7-2 compressors in CMOS process for rapid parallel accumulations,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 28, No. 6, pp. 1403-1412, 2020.
[22] Amir Fathi, Sarkis Azizian, Khayrollah Hadidi and Abdollah Khoei, “A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations,” IEICE transactions on electronics, Vol. 95, No. 4, pp. 710-712, April 2012.