Full adder

Open Access Article

1 - Design of Low Power Single-Bit Full-Adder Cell Based on Pass-Transistor Logic
Mehdi Sayyaf Abdolrasool Ghasemi Roozbeh Hamzehyan

10.30495/jce.2022.692834

In today's electronic and digital world, increasing demand for portable systems has led the electronics industry and chip design technology to reduce power consumption methods, and therefore power consumption has become an important criterion in this field. Also, increa More

In today's electronic and digital world, increasing demand for portable systems has led the electronics industry and chip design technology to reduce power consumption methods, and therefore power consumption has become an important criterion in this field. Also, increasing the speed of chips and reducing the propagation delay of circuits has always been an important goal of digital design engineers. Since the Adder element is one of the important elements in many digital systems, so today various Adders with different technologies and design approaches have been proposed, each of which has certain advantages and disadvantages. This paper presents a low-power single-bit full-adder cell design that is based on pass-transistor logic.This circuit is used in the arithmetic logic units of digital signal processors and also in several electronic and digital communication systems that operate within the frequency range of in 1GHz. The proposed cell exploits the pass transistor techniques and XOR-XOR structures to improve the design parameters namely power consumption, propagation delay, power–delay product, and the number of transistors. The proposed circuit is designed using 180nm CMOS technology and the simulation results show that for a supply voltage of 1.8V, the power consumption, delay, and power–delay product have been achieved as 83 W, 89ps, and 7fJ respectively. Manuscript profile

Open Access Article

2 - Low Latency and Power Efficient Reversible Full Adder based on Toffoli Gates
Seyedeh Fatemeh Deymad Nabiollah Shiri Farshad Pesaran

10.30495/jce.2023.1988197.1207

The reversible circuits are useful in energy-saving applications because of their unique features. Hence, using 32 nm carbon nanotube field-effect transistor (CNTFET) technology and relying on Toffoli's reversible gates, a new full adder (FA) circuit is presented. The p More

The reversible circuits are useful in energy-saving applications because of their unique features. Hence, using 32 nm carbon nanotube field-effect transistor (CNTFET) technology and relying on Toffoli's reversible gates, a new full adder (FA) circuit is presented. The proposed circuit has 4 basic Toffoli gates and 18 transistors. 3 of the 4 gates have the same transistor schematic with a constant-ON transistor, but the remaining gate has only two transistors. The proposed circuit has 3 constant inputs and 4 garbage outputs. As a new method, in the proposed circuit, only one type of reversible gate is used. The results show the superiority of the proposed FA in terms of power consumption and energy dissipation. By implementing the proposed FA and other circuits in a 4-bit and 8-bit ripple carry adder (RCA), the proposed circuit shows improvements by 6.83% and 11.25% in terms of power and energy, respectively, compared to the main competitor. Also, in an 8-bit RCA, the proposed FA has a 2% saving compared to the nearest competitor and 27% compared to the worst circuit in terms of the power-delay-area-product (PDAP). These results show the designed FA as a favorable option for complex structures with high-order bits. Manuscript profile

Open Access Article

3 - A Multiplier-Less Discrete Cosine Transform Architecture Using a Majority Logic-Based Approximate Full Adder
Elham Esmaeili Farshad Pesaran Nabiollah Shiri

10.30495/jce.2023.1988087.1206

This paper proposes a new approximate full adder (FA) based on the majority logic (ML) concept. The fundamental structure of the ML concept is a 3-input majority voter and is widely utilized in digital arithmetic cells. The ML-based proposed FA works at low power, small More

This paper proposes a new approximate full adder (FA) based on the majority logic (ML) concept. The fundamental structure of the ML concept is a 3-input majority voter and is widely utilized in digital arithmetic cells. The ML-based proposed FA works at low power, small delay, and low power-delay-product (PDP). The carbon nanotube field-effect transistor (CNTFET) technology lowers the FA power, while the gate diffusion input (GDI) technique is used as the main technique. The swing issue of the GDI technique is resolved by the dynamic threshold (DT) technique. Compared with its exact circuit, the proposed FA saves 2 majority gates, 3 inverters, and a 4.02 ns delay. In the proposed FA, the PDP is improved by 53.73%. The product of the PDP and the normalized mean error distance (NMED) is called PDPE, and in the presented FA, it is reduced by 9.50%. Moreover, the proposed FA is embedded into a multiplier-less discrete cosine transform (DCT) design, which is an appropriate circuit for very large-scale integration (VLSI) systems. The 8-input DCT architecture consumed 2.2321 mW of power for each DCT operation. Also, the circuit has better performance in terms of PDP-area-product (PDAP). The results of DCT implementations confirm the efficiency of the FA. Manuscript profile

Open Access Article

4 - Evaluation of Temperature, Disturbance and Noise Effect in Full Adders Based on GDI Method
Hashem Arfavi Seyed Mohammadali Riazi Roozbeh Hamzehyan

10.30495/jce.2023.1973764.1197

In this paper, we limit our attention to full adders based on the GDI method, circuits that are commonly used in high-speed circuits and are more prone to noise. So far, a comprehensive review on noise immunity and ambient temperature change of full adders based on the More

In this paper, we limit our attention to full adders based on the GDI method, circuits that are commonly used in high-speed circuits and are more prone to noise. So far, a comprehensive review on noise immunity and ambient temperature change of full adders based on the GDI method has not been presented, and most of the studies have compared their proposed design with other full adders, which are mainly not based on the GDI method. These full adder cells were evaluated by various simulations such as supply voltage change, capacitive load change, ambient temperature change and process-voltage-temperature (PVT) changes in 45 nm CMOS technology. A noise immunity curve (NIC) was derived for full adder cells to identify better-performing full adder cells. The unity noise gain (UNG) was also investigated to evaluate the noise. Finally, a comprehensive comparison was made in terms of propagation delay, power consumption, power-delay product (PDP), voltage swing, sensitivity to process changes and noise for full adders based on the GDI method. The obtained results can be useful in the decisions of integrated circuit designers to choose the appropriate structure of the full adder based on the GDI method Manuscript profile

Open Access Article

5 - Analysis of the effect of changes of FINs Architectural on FINFET Drain current and on Average Power Dissipation and Propagation Delay in the Hybrid-CMOS full adder
Teimoor Rashedzadeh Seyed Mohammad Ali Riyazi Najmeh Cheraghi Shirazi

In this paper, full adder circuit with Hybrid-CMOS logic style is proposed which is a combination of pass transistors and transmission gates and N & P type transistors. For design full adder circuitry using FINFET transistors, BSIM-CMG model, Dual-gate and bulk FINF More

In this paper, full adder circuit with Hybrid-CMOS logic style is proposed which is a combination of pass transistors and transmission gates and N & P type transistors. For design full adder circuitry using FINFET transistors, BSIM-CMG model, Dual-gate and bulk FINFET structure using 16nm Gate length and HSPICE simulation. due to the structure and architecture of the FINFET transistors, the effect of changes in thickness and height and the number of FINs on the Drain current of the FINFET transistor and output parameters such as average power dissipation and propagation delay of the full adder cell and also the effect of changes in inputs frequency of full adder are investigated. According to the simulation results, with increasing thickness and height and the number of FINs, average power dissipation increases and propagation delay decreases, and vice versa. As well as increasing the operating frequency up, average power dissipation increases. Manuscript profile

Open Access Article

6 - A New Coplanar Full Adder/Subtractor in Quantum-Dot Cellular Automata Technology
Mohsen Vahabi Amir Sabbagh Molahosseini

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Open Access Article

7 - An Ultra-Low-Power and Full-Swing Full Adder Cell
Soorena Zohoori Mehdi Dolatshahi

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Open Access Article

8 - Design and Simulation of Low Power Adder Circuits Using MGDI Gate in QCA Technology
Hamidreza Sadrarhami Sayed Mohammadali Zanjani Mehdi Dolatshahi Behrang Barekatain

With the design of circuits at the nano-scale and observation of the problems of CMOS technology, designers are seeking suitable alternatives for this technology. Quantum-dot Cellular Automata (QCA) is one of these proposed technologies, which has attracted researchers' More

With the design of circuits at the nano-scale and observation of the problems of CMOS technology, designers are seeking suitable alternatives for this technology. Quantum-dot Cellular Automata (QCA) is one of these proposed technologies, which has attracted researchers' attention due to its high speed and low power consumption. On the other hand, the Gate Diffusion Input (GDI) method is an approach to improve power and area efficiency, which has led to higher speed, less power loss, and reduced complexity in Boolean functions through the use of fewer transistors. Furthermore, the adder, as a fundamental computational circuit in the design of digital systems, is of special importance. In this paper, a half-adder circuit, a half-subtractor circuit, and three new adder circuits in QCA technology have been designed and improved with the help of the GDI block. Simulation of these circuits using the QCADesigner software in 18-nanometer technology demonstrates the advantages of simultaneously using QCA technology and the GDI method. The results of the comparison and evaluation of the proposed circuits relative to the best existing adder indicate a reduction of about 55% in the occupied area, a significant decrease in the number of cells, and a delay that is equal to or less than 28% compared to existing works. Manuscript profile

Open Access Article

9 - A New 2-input CNTFET-Based XOR Cell With Ultra-Low Leakage Power For Low-Voltage and Low-Power Full Adders
Amir Baghi Rahin Vahid Baghi Rahin

The XOR gate is one of the basic building blocks in the Full Adder (FA) circuit, whose performance improvements can lead to improved Full Adder. For this purpose, in this paper, a new low voltage XOR cell based on Carbon Nanotube Field Effect Transistor (CNTFET) is prop More

The XOR gate is one of the basic building blocks in the Full Adder (FA) circuit, whose performance improvements can lead to improved Full Adder. For this purpose, in this paper, a new low voltage XOR cell based on Carbon Nanotube Field Effect Transistor (CNTFET) is proposed. The main design goals for this new circuit are low power dissipation, low leakage current and full voltage swing at a low supply voltage (Vdd = 0.5 V). Several XOR circuits were completely simulated using HSPICE with 32nm CMOS and 32nm CNTFET technologies at a low supply voltage. The proposed XOR circuit is compared with the previously known circuits and its outstanding performance is shown. Simulations show that the new low voltage XOR has lower power dissipation, less leakage current and lower PDP than other XOR circuits, and is resistant to process variations. Based on the results obtained at Vdd=0.5 V ,frequency=250 MHz and Cload=3.5 fF, the proposed XOR shows propagation delay of 149.05 ps, power consumption of 716.72 pW, leakage power of 25.1 pW and PDP of 10.683x10-21 J. The proposed XOR can be used well in low voltage and low power Full Adder circuits. Manuscript profile

Open Access Article

10 - Ultra low voltage and low power 4-2 compressor using FinFET transistors
Amir Baghi Rahin Vahid Baghi Rahin

A compressor is basic building blocks of many arithmetic circuits. Design of smaller area, low power consumption and high speed compressor is always in demand. As the channel length approaches nanometer scale, the use of MOSFET as the basic device in compressor now has More

A compressor is basic building blocks of many arithmetic circuits. Design of smaller area, low power consumption and high speed compressor is always in demand. As the channel length approaches nanometer scale, the use of MOSFET as the basic device in compressor now has reaching its performance limits such as average power dissipation and speed. In this paper, a 1-bit full adder cell using FinFET transistor based on PTM 32nm process model with 0.6 V supply voltage for mobile applications is proposed. Then, the proposed full adder cell is used in the structure of compressor and performance of the proposed 4: 2 compressor is evaluated with the simulation results obtained from HSPICE. The main parameters of proposed compressor such as power compression, delay, power-delay product (PDP) and energy-delay product (EDP) were measured and its superior performance has been proved by various simulations. Also, in comparison of MOSFET based compressor, the number of transistors is decreased to 42. Manuscript profile

Open Access Article

11 - Design and Simulation of a New Optimized Full-Adder Using Carbon Nano Tube Technology
Abbas Asadi Aghbolaghi Mehran Emadi

The full adder circuit is one of the most significant and prominent fundamental parts in digital processors and integrated circuits since it can be used for implementing all four basic computational functions including: addition, subtraction, multiplication, and divisio More

The full adder circuit is one of the most significant and prominent fundamental parts in digital processors and integrated circuits since it can be used for implementing all four basic computational functions including: addition, subtraction, multiplication, and division. so, in this paper a new low power and high performance full adder cell has been proposed with the benefit of using carbon nano tube field effect transistors. The proposed design contains 12 CNTFET transistors which are connected in pass transistor logic style to make the desired functionality. Carbon Nano Tube Field Effect Transistor (CNTFET) has modified electrical characteristics such as low power consumption and high speed in comparison with MOSFET transistor; The proposed design is simulated using Hspice software based on CNTFET model and 0.65V supply voltage. the simulations are done considering three different frequencies, and three different load capacitors. The simulation results, which demonstrated in tables and diagrams, proved the superiority of proposed design in terms of power consumption and performance (PDP) compared to the existing counterparts. Manuscript profile

Open Access Article