List of Articles field effect transistor

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  1 - First principle study of the effect of defects on performance of single-molecule pentacene field effect transistors
  Bahniman Ghosh Akash Gramin
  10.1007/s40094-015-0182-8
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  2 - Design and simulation of an Improved NEMFET with Low Leakage Current and Sub-threshold Swing
  Nastaran Jafari Farshad Babazadeh Zahra Ahangari
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  3 - Performance Investigation of Pentacene Based Organic Double Gate Field Effect Transistor and its Application as an Ultrasensitive Biosensor
  Mohammad Reza Jouharchi Zahra Ahangari Farshad Babazadeh
  10.22034/jna.2020.1884903.1177
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  4 - Performance Optimization and Sensitivity Analysis of Junctionless FinFET with Asymmetric Doping Profile
  Zahra Ahangari Ehsan Asadi Seied Ali Hosseini
  10.22034/jna.2020.1898545.1208
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  5 - A New 2-input CNTFET-Based XOR Cell With Ultra-Low Leakage Power For Low-Voltage and Low-Power Full Adders
  Amir Baghi Rahin Vahid Baghi Rahin
  The XOR gate is one of the basic building blocks in the Full Adder (FA) circuit, whose performance improvements can lead to improved Full Adder. For this purpose, in this paper, a new low voltage XOR cell based on Carbon Nanotube Field Effect Transistor (CNTFET) is prop More

  The XOR gate is one of the basic building blocks in the Full Adder (FA) circuit, whose performance improvements can lead to improved Full Adder. For this purpose, in this paper, a new low voltage XOR cell based on Carbon Nanotube Field Effect Transistor (CNTFET) is proposed. The main design goals for this new circuit are low power dissipation, low leakage current and full voltage swing at a low supply voltage (Vdd = 0.5 V). Several XOR circuits were completely simulated using HSPICE with 32nm CMOS and 32nm CNTFET technologies at a low supply voltage. The proposed XOR circuit is compared with the previously known circuits and its outstanding performance is shown. Simulations show that the new low voltage XOR has lower power dissipation, less leakage current and lower PDP than other XOR circuits, and is resistant to process variations. Based on the results obtained at Vdd=0.5 V ,frequency=250 MHz and Cload=3.5 fF, the proposed XOR shows propagation delay of 149.05 ps, power consumption of 716.72 pW, leakage power of 25.1 pW and PDP of 10.683x10-21 J. The proposed XOR can be used well in low voltage and low power Full Adder circuits. Manuscript profile
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  6 - Design and Simulation of a Bulk Driven Operational Transconductance Amplifier Based on CNTFET Technology
  Sayed Mohammad Ali Zanjani Mostafa Parvizi
  In this paper, a new two-stage OTA is proposed which meeting the needs of high gain, low power and low noise, and designed based on the gm/ID technique with bulk driven method. It is noteworthy that due to the limitations of CMOS technology, CNTFET technology used for t More

  In this paper, a new two-stage OTA is proposed which meeting the needs of high gain, low power and low noise, and designed based on the gm/ID technique with bulk driven method. It is noteworthy that due to the limitations of CMOS technology, CNTFET technology used for the circuit designs. Moreover, to improve the linearity of the circuit, triode transistors used in both stages of amplifiers. The simulation results of the proposed OTA are performed under 1V of supply voltage and 1pF of load capacitors in the HSPICE tool. According to the simulation results, the proposed circuit consumes less than 27 µW of power and offers a high gain of 98 dB. The CMRR and PSRR values of the proposed circuit are 121 dB and 152 dB, respectively. The input referred noise is 0.92 nV/√Hz and the slew rate of the proposed circuit is 111 V/µs, which shown the better figure of merit (FOM) in compression with the previous works.   Manuscript profile
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  7 - Design of a Low Power Temperature Sensor Based on Sub-Threshold Performance of Carbon Nanotube Transistors with an Inaccuracy of 1.5ºC for the range of -30 to 125ºC
  Sayed Mohammad Ali Zanjani Masoumeh Aalipour Mostafa Parvizi
  In this paper, a new temperature sensor based on the performance of carbon nanotube transistors in the subthreshold region is designed and simulated which leads to reduction of power consumption. Also, a differential amplifier is used in the output of the sensor. in ord More

  In this paper, a new temperature sensor based on the performance of carbon nanotube transistors in the subthreshold region is designed and simulated which leads to reduction of power consumption. Also, a differential amplifier is used in the output of the sensor. in order to keep the values of gain and common mode level voltage due to temperature changes, a method has been proposed that can compensate for these parameters variation due to temperature variation in the range of -30 ºC to +125 ºC. The proposed temperature sensor with its amplifier can be used as a system on the chip surface for temperature monitoring and control. The proposed temperature sensor in the CNTFET carbon nanotube field effect transistor technology with a supply voltage of 0.5 V in the sub-threshold area is simulated by HSPICE software with a 32nm CNT model. The simulation results show that at proposed circuits can measure the temperature in range of -30 ºC to +125 ºC linearly with a sensitivity of 1 mV/ ºC and consumes only 123 nW at room temperature. Also, the error measured at 125 ºC is about 2.5 mV, which means an error of 1.25 ºC at this temperature. Manuscript profile
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  8 - Design and Simulation of a New Optimized Full-Adder Using Carbon Nano Tube Technology
  Abbas Asadi Aghbolaghi Mehran Emadi
  The full adder circuit is one of the most significant and prominent fundamental parts in digital processors and integrated circuits since it can be used for implementing all four basic computational functions including: addition, subtraction, multiplication, and divisio More

  The full adder circuit is one of the most significant and prominent fundamental parts in digital processors and integrated circuits since it can be used for implementing all four basic computational functions including: addition, subtraction, multiplication, and division. so, in this paper a new low power and high performance full adder cell has been proposed with the benefit of using carbon nano tube field effect transistors. The proposed design contains 12 CNTFET transistors which are connected in pass transistor logic style to make the desired functionality. Carbon Nano Tube Field Effect Transistor (CNTFET) has modified electrical characteristics such as low power consumption and high speed in comparison with MOSFET transistor; The proposed design is simulated using Hspice software based on CNTFET model and 0.65V supply voltage. the simulations are done considering three different frequencies, and three different load capacitors. The simulation results, which demonstrated in tables and diagrams, proved the superiority of proposed design in terms of power consumption and performance (PDP) compared to the existing counterparts. Manuscript profile
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  9 - Design and Implementation of MOSFET Circuits and CNTFET, Ternary Multiplier in the Field of Galois
  Malakeh Karimghasemi-rabori Peiman Keshavarzian
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  10 - A Low Power Full Adder Cell based on Carbon Nanotube FET for Arithmetic Units
  Mokhtar Mohammadi Ghanatghestani Mehdi Bagherizadeh
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  11 - Performance Analysis of InAs/AlGaSb Heterojunction Electron-Hole Bilayer Tunnel Field Effect Transistor for Low-Power High-Speed Digital Computing
  Zahra Ahangari
  10.30495/ijsee.2023.1988303.1268
  In this paper, a novel device, namely heterojunction electron-hole bilayer tunnel field effect transistor (HJ-EHBTFET), is proposed which outperforms conventional tunnel field effect transistor (TFET) in terms of electrical performance. The use of lattice matched InAs/A More

  In this paper, a novel device, namely heterojunction electron-hole bilayer tunnel field effect transistor (HJ-EHBTFET), is proposed which outperforms conventional tunnel field effect transistor (TFET) in terms of electrical performance. The use of lattice matched InAs/Al0.6Ga0.4Sb material combination results in a broken band gap configuration, making it highly suitable for high speed ultra-low applications, as it requires smaller gate bias for the onset of tunneling. The impact of critical design parameters on the device performance is comprehensively investigated. The proposed device utilizes electrical doping instead of physical doping for the creation of tunneling junction, which effectively addresses the problem of low solubility of dopants in heavily doped III-V materials. The top gate and bottom gate workfunction are critical design parameters that effectively modulated the electrically induced charges at the tunneling junction and consequently, affect the tunneling rate. In order to obtain the lowest possible transition voltage for the onset of tunneling, a variation matrix of threshold voltage variation is computed as a function of gate electrode workfunction. Through this process, a step-like behavior from off-state to on-state has been achieved, with a subthreshold swing of 3 mV/dec and on/off current ratio of 5.8×1012, thereby paving the way for the design of low-power high-speed digital computing systems. Manuscript profile