Subject Areas : Journal of Optoelectronical Nanostructures

Zahra Ahangari ¹ (Department of Electronic, Faculty of Electrical Engineering, Yadegar- e- Imam Khomeini (RAH) Shahr-e-Rey Branch, Islamic Azad University, Tehran, Iran.)

Received: 2020-03-31 Accepted : 2020-07-04 Published : 2020-05-01

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REFERENCES
[1] Lin, Huang-Hsuan, and Yuan Taur. Effect of source–drain doping on subthreshold characteristics of short-channel DG MOSFETs. IEEE Transactions on Electron Devices 64, no. 12 (2017): 4856-4860.
[2] Bahrami, P., Shayesteh, M., Pourahmadi, M., Safdarkhani, H. Improvement of the Drive Current in 5nm Bulk-FinFET Using Process and Device Simulations. Journal of Optoelectronical Nanostructures, (2020); 5(1): 65-82.
[3] Nayeri, M., keshavarzian, P., Nayeri, M. A Novel Design of Penternary Inverter Gate Based on Carbon Nano Tube. Journal of Optoelectronical Nanostructures, (2018); 3(1): 15-26.
Switching Performance of Nanotube Core-Shell Heterojunction Electrically Doped … * 11
[4] Pourchitsaz, K., Shayesteh, M. Self-heating effect modeling of a carbon nanotube-based fieldeffect transistor (CNTFET). Journal of Optoelectronical Nanostructures, (2019); 4(1): 51-66.
[5] Roohy, M., Hosseini, R. Performance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor. Journal of Optoelectronical Nanostructures, (2019); 4(2): 13-28.
[6] Kwon, Daewoong, Korok Chatterjee, Ava J. Tan, Ajay K. Yadav, Hong Zhou, Angada B. Sachid, Roberto Dos Reis, Chenming Hu, and Sayeef Salahuddin. Improved subthreshold swing and short channel effect in FDSOI n-channel negative capacitance field effect transistors. IEEE Electron Device Letters 39, no. 2 (2017): 300-303.
[7] Avci, Uygar E., and Ian A. Young. Heterojunction TFET scaling and resonant-TFET for steep subthreshold slope at sub-9nm gate-length. In 2013 IEEE International Electron Devices Meeting, pp. 4-3. IEEE, 2013.
[8] Raad, B., K. Nigam, D. Sharma, and P. Kondekar. Dielectric and work function engineered TFET for ambipolar suppression and RF performance enhancement. Electronics Letters 52, no. 9 (2016): 770-772.
[9] Wang, Hongjuan, Genquan Han, Xiangwei Jiang, Yan Liu, Jincheng Zhang, and Yue Hao. Improved performance in GeSn/SiGeSn TFET by hetero-line architecture with staggered tunneling junction. IEEE Transactions on Electron Devices 66, no. 4 (2019): 1985-1989.
[10] Yan, Zhirui, Cong Li, Jiamin Guo, and Yiqi Zhuang. A GaAs0.5Sb0.5/In0.53Ga0.47As heterojunction Z-gate TFET with hetero-gate-dielectric. Superlattices and Microstructures 129 (2019): 282-293.
[11] Datta, E., Chattopadhyay, A., Mallik, A. and Omura, Y., Temperature dependence of analog performance, linearity, and harmonic distortion for a ge-source tunnel FET. IEEE Transactions on Electron Devices, 67(3), (2020), pp.810-815.
[12] Long, Y., Huang, J.Z., Huang, Q., Xu, N., Jiang, X., Niu, Z.C., Huang, R. and Li, S.S., Piezoelectric Tunnel FET With a Steep Slope. IEEE Electron Device Letters, 41(6), (2020), pp.948-951.
[13] Singh, A., Kumar, N., Amin, S.I. and Anand, S., Implementation of negative capacitance over SiGe sourced Doping-less Tunnel FET. Superlattices and Microstructures, (2020), p.106580.
[14] Joseph, H. Bijo, Sankalp Kumar Singh, R. M. Hariharan, Yusuf Tarauni, and D. John Thiruvadigal. Simulation study of gated nanowire InAs/Si Hetero p channel TFET and effects of interface trap. Materials Science in Semiconductor Processing 103 (2019): 104605.
12 * Journal of Optoelectronical Nanostructures Spring 2020 / Vol. 5, No. 2
[15] Damrongplasit, Nattapol, Sung Hwan Kim, and Tsu-Jae King Liu. Study of random dopant fluctuation induced variability in the raised-Ge-source TFET. IEEE electron device letters 34, no. 2 (2013): 184-186.
[16] Damrongplasit, Nattapol, Sung Hwan Kim, Changhwan Shin, and Tsu-Jae King Liu. Impact of gate line-edge roughness (LER) versus random dopant fluctuations (RDF) on germanium-source tunnel FET performance. IEEE transactions on nanotechnology 12, no. 6 (2013): 1061-1067.
[17] Chandan, Bandi Venkata, Kaushal Nigam, Vinay Anand Tikkiwal, and Dheeraj Sharma. Impact of Hetero Dielectric on the Device Electrical and Linearity Characteristics of Electrically Doped Tunnel FET. Advanced Science, Engineering and Medicine 11, no. 6 (2019): 484-490.
[18] Chandan, Bandi Venkata, Kaushal Nigam, Pravin Kondekar, and Dheeraj Sharma. Approach to suppress the ambipolar current conduction and improve radiofrequency performance in polarity control electrically doped hetero TFET. Micro & Nano Letters 14, no. 10 (2019): 1033-1036.
[19] Kumar, Naveen, Umar Mushtaq, S. Intekhab Amin, and Sunny Anand. Design and performance analysis of dual-gate all around core-shell nanotube TFET. Superlattices and Microstructures 125 (2019): 356-364.
[20] Yoon, Jun-Sik, Kihyun Kim, M. Meyyappan, and Chang-Ki Baek. Bandgap engineering and strain effects of core–shell tunneling field-effect transistors. IEEE Transactions on Electron Devices 65, no. 1 (2017): 277-281.
[21] Gupta, Ashok Kumar, Ashish Raman, and Naveen Kumar. Design and investigation of a novel charge plasma-based core-shell ring-TFET: analog and linearity analysis. IEEE Transactions on Electron Devices 66, no. 8 (2019): 3506-3512.
[22] Ahangari, Zahra. Performance investigation of steep-slope core–shell nanotube indium nitride electron–hole bilayer tunnel field effect transistor. Applied Physics A 125, no. 6 (2019): 405.
[23] ATLAS User Manual, Santa Clara, USA: Silvaco International, 2015.