This paper investigates the effects of the uniaxial tensile strain on the performance of an all silicon junction-less tunneling field-effect transistor (JLTFET) for analog and digital applications. The behavior of the JLTFET under global and local uniaxial strain are studied based on the energy band diagram at ON, OFF, and ambipolar states. Under local uniaxial tensile strain, it has been observed that the tunneling length at the channel/source interface in the ON state has been decreased and at the channel/drain interface in the OFF state has been increased. Simulations illustrate improvements in ON current, ION/IOFF and steep sub threshold swing (SS) and superior transconductance (gm). The strained JLTFET, also demonstrates capability for low-voltage application and high cut-off frequency (fT) and suppressed ambipolar current (Iamb). تفاصيل المقالة

In this paper, we propose an innovative and low computational cost approach that can be used to find optimal values of parameters of a nanoscale dual gate tunneling field-effect transistor (DG-TFET). In this way, after obtaining analytical expressions for potential and energy bands of the device using the Poisson equation, the tunneling length is extracted at source-channel and channel-drain tunnel junctions in the AMBIPOLAR, Off and On states. Due to the tunneling length equation, the different values of gate work function and dielectric constant of the device are swept to determine the minimum and maximum design limits. According to the above range, the necessary checks are made to reach the local optimal behaviors. These optimum points are explained based on the achievement of optimal device performance. The accuracy and consistency of the proposed model is validated with the TCAD simulation results. The present model can be a handful for the study of TFET performance. تفاصيل المقالة

In this paper, a new Nano-Scale structure of dual material gate oxide stack-double gate TFET (DMGOS-DG TFET) with the inclusion of the dielectric pocket (DP) in the drain region is proposed. Hence the gate consists of three parts, named M1, M2, and M3 with work functions ϕM1, ϕM2, and ϕM3 respectively. The work function engineering with the gate oxide stack (SiO2 as the bottom layer and HfO2 as the top layer) improves ON current, leakage current, and ambipolar behavior. In addition, the dielectric pocket (DP) has been used in the drain region to achieve better ambipolar performance. Moreover, it is found that in comparison with the low-k DP (SiO2), the presence of the high-k DP (HfO2) provides a lower ambipolar current due to the greater depletion width in the drain region. Furthermore, the ambipolar behavior of the DP-DMGOS-DG TFET structure has been investigated by changing the length and thickness of the high-k DP. Finally, the comparative analysis of DMGOS-DGTFET and high-k DP-DMGOS-DG TFET on high-frequency performance reveals that DP inclusion reduces the gate-to-drain capacitance, which leads to the improved cut-off frequency. تفاصيل المقالة

In this paper, we propose an innovative and low computational cost approachthat can be used to find optimal values of parameters of a nanoscale dual-gatea tunneling field-effect transistor (DG-TFET). In this way, after obtaining analyticalexpressions for potential and energy bands of the device using the Poissonequation, the tunneling length is extracted at source-channel and channel-draintunnel junctions in the AMBIPOLAR, Off and On states. Due to the tunnelinglength equation, the different values of gate work function and dielectric constantof the device are swept to determine the minimum and maximum designlimits. According to the above range, the necessary checks are made to reachthe local optimal behaviors. These optimum points are explained based on theachievement of optimal device performance. The accuracy and consistency of theproposed model are validated with the TCAD simulation results. The present modelcan be a handful for the study of TFET performance. تفاصيل المقالة

In this paper, we propose an innovative and low computational cost approachthat can be used to find optimal values of parameters of a nanoscale dual gatetunneling field-effect transistor (DG-TFET). In this way, after obtaining analyticalexpressions for potential and energy bands of the device using the Poissonequation, the tunneling length is extracted at source-channel and channel-draintunnel junctions in the AMBIPOLAR, Off and On states. Due to the tunnelinglength equation, the different values of gate work function and dielectric constantof the device are swept to determine the minimum and maximum designlimits. According to the above range, the necessary checks are made to reachthe local optimal behaviors. These optimum points are explained based on theachievement of optimal device performance. The accuracy and consistency ofthe proposed model are validated with the TCAD simulation results. The presentmodel can be a handful for the study of TFET performance. تفاصيل المقالة