low noise

Open Access Article

1 - Designing a Low Power Low Noise Amplifier for Global Positioning System (GPS) Standard Based on Simulation and Mathematical Relationships
Mozhgan Javahernia Sahel Javahernia

10.30495/jce.2023.1981190.1194

Today, one of the most important issues in mobile communication systems is having a long battery life. Therefore, the problem of power consumption appears as one of the challenges in the field of designing high frequency circuits. In a high-frequency receiver, due to th More

Today, one of the most important issues in mobile communication systems is having a long battery life. Therefore, the problem of power consumption appears as one of the challenges in the field of designing high frequency circuits. In a high-frequency receiver, due to the placement of the low-noise amplifier in the first stage of the receiver, this amplifier is very important to determine the linearity and noise in the entire receiver. In this paper, a low noise amplifier has been designed for the GPS standard. Compared to previous works, the noise of the amplifier has been reduced somehow, and its power consumption has reached its minimum value. The working method is that in common source amplifiers, their source base is connected with an inductor, which results in improving circuit noise. But the used inductor occupies the surface of the chip. Therefore, in this article, the existence of the inductor in wire-bond is used, and the noise of the amplifier is reduced, and the occupied area of the chip is not increased. Gain, NF, input impedance of the proposed amplifier have been calculated in the best case and the worst case in the corners of FF and SS, and it can be seen that in this article, compared to the previous works, very favorable results have been obtained. Manuscript profile

Open Access Article

2 - Low noise amplifier with active induction load CMOS
Babak Gholami Shahriyar Bazyari Khashayar Bazyari

This article presents a common low-noise CMOS gate amplifier with active induction load. For large amounts of inductance, a passive inductor on the chip requires a significant area of the chip and its quality factor is limited. A situation that can be considered impract More

This article presents a common low-noise CMOS gate amplifier with active induction load. For large amounts of inductance, a passive inductor on the chip requires a significant area of the chip and its quality factor is limited. A situation that can be considered impractical. Therefore, the purpose of this work is to search for the possibility of using active inductors in RF circuits as a substitute for their inactive counterpart. In addition, this active inducer is programmable. It is possible to design an amplifier with a programmable central frequency. It is also shown that with proper and optimal design, the contribution of active inductor noise can be minimized. HSPICE simulation using 0.35 µm technology showed that our amplifier has a half-decade tuning range for 1GHz. The gain, noise number and power consumption of the simulated are 20dB, 3.65dB, 14mw, respectively. Manuscript profile

Open Access Article

3 - Design and simulation of low power dual band low noise amplifier for wireless LAN applications
Omid Eslamifar Maryam Eslamifar

 The following paper presents the design and simulation of a low-noise amplifier (LNA) using complementary low power-metal oxide (CMOS) transistors for LAN applications (WLAN 802.11). Input The external capacitor switch connected to the gate-source transistor input More

 The following paper presents the design and simulation of a low-noise amplifier (LNA) using complementary low power-metal oxide (CMOS) transistors for LAN applications (WLAN 802.11). Input The external capacitor switch connected to the gate-source transistor input node is used in 2 bands of 4.2 and 2.5 GHz. In simultaneous structures using the resonant frequency of the LC tank circuit, the desired frequency is selected, while in the proposed LNA structure, this frequency selection is done only by adding a capacitive switch to the normal degenerate source structure. This reduces the occupied space. It has structures in the circuit compared to others. In addition, the use of the transistor switch technique reduces the power consumption compared to other structures LNA. The offer has a 1 volt power supply and a current of 3.2 mA. The circuit has scattering parameters S11 and S22 less than 19 dB in both frequency bands and has noise numbers of 3.2 and 3.5 dB at 4.2 and 2.5 GHz, respectively. Power output is greater than 20 dB Manuscript profile

Open Access Article

4 - A 3.1-10.6 GHZ Ultra-Wideband CMOS Low Noise Amplifier in 0.18 μm CMOS Technology
Meysam Azimi-Roein

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Open Access Article

5 - Design and Simulation of X Band LNA for Aircraft Receiver
mehdi Samadi ali rostami ali sahafi

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Open Access Article

6 - A W-band Simultaneously Matched Power and Noise Low Noise Amplifier Using CMOS 0.13µm
Mahmoud Mohammad-Taheri

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Open Access Article

7 - A review on power reducing methods of neural recording amplifiers
samira mehdipour mehdi habibi

Implantable multi-channel neural recording Microsystems comprise a large number of neural amplifiers, that can affect the overall power consumption and chip area of the analog part of the system.power, noise, size and dc offset are the main challenge faced by designers. More

Implantable multi-channel neural recording Microsystems comprise a large number of neural amplifiers, that can affect the overall power consumption and chip area of the analog part of the system.power, noise, size and dc offset are the main challenge faced by designers. Ideally the output of the opamp should be at zero volts when the inputs are grounded.In reality the input terminals are at slightly different dc potentials.The input offset voltage is defined as the voltage that must be applied between the two input terminals of the opamp to obtain zero volts at the output. Amplifier must have capability to reject this dc offset. First method that uses a capacitor feedback network with ac coupling of input devices to reject the offset is very popular in designs.very small low-cutoff frequency.The second method employs a closed-loop resistive feedback and electrode capacitance to form a highpass filter.Moreover,The third method adopts the symmetric floating resistor the feedback path of low noise amplifier to achieve low-frequency cutoff and rejects DC offset voltage. .In some application we can use folded cascade topology.The telescopic topology is a good candidate in terms of providing large gain and phase margin while dissipating small power. the cortical VLSI neuron model reducing power consumption of circuits.Power distribution is the best way to reduce power, noise and silicon area. The total power consumption of the ampliﬁer array is reduced by applying the partial OTA sharing technique. The silicon area is reduced as a beneﬁt of sharing the bulky capacitor Manuscript profile

Open Access Article

8 - Design and simulation of a low-noise low-power narrowband amplifier (LNA) in 180 nm CMOS technology
Esmail Karimi

Abstrac: In this paper presented discussed to design a low noise amplifier (LNA) with inductor at source in TSMC 0.18um CMOS technology to 2.4 GHz. Cascode structure cause reduces the power consumption of the circuit[1]; the advantage of using cascade structure, increas More

Abstrac: In this paper presented discussed to design a low noise amplifier (LNA) with inductor at source in TSMC 0.18um CMOS technology to 2.4 GHz. Cascode structure cause reduces the power consumption of the circuit[1]; the advantage of using cascade structure, increase the output impedance of the circuit impedance increases, increasing the circuit to follow. The circuit presented in this article a low noise amplifier cascoded with inductor in the source along with impedance matching network added in the input and output; and led to 1.6db noise figure and power consumption of 2.1mw achieved, respectively. Add matching networks to a greater degree of freedom in circuit for improved noise figure and power consumption and chip internal area is also reduced. Add the rest of the circuit in addition to reducing power and noise figure considerations in mind we have been able in the desired frequency and reflection coefficient in the input circuit respectively 20db and -12db achieved. Manuscript profile

Open Access Article

9 - System Design of a Low-power Non-coherent Receiver for Stimulating Wireless Neural Implants
Fakhralsadat Rastegari Massoud Dousti Behbod Ghalamkari

In recent years, low-power transceivers have found wide applications in medical engineering. In this paper, the system design and simulation of a low-power implantable receiver are presented for the case of stimulating brain cells. The receiver shows a high data rate in More

In recent years, low-power transceivers have found wide applications in medical engineering. In this paper, the system design and simulation of a low-power implantable receiver are presented for the case of stimulating brain cells. The receiver shows a high data rate in the industrial scientific and medical (ISM) band for being used in a bidirectional wireless full-duplex link and communication between the implanted system and the outside world. The proposed receiver has a non-coherent structure and operates at a frequency of 2.4 GHz with on-off keying (OOK) modulation. This receiver has a bit error rate (BER) of less than 0.001 and a data rate of 100 Mbps. The simulation results of the proposed circuit show a 26.4 dB gain (S21), a -39 dB input return loss (S11) and a 5.22 dB noise figure (NF). The simulation results are in good agreement with the analytical calculations. Manuscript profile

Open Access Article

10 - A Novel Resistive Capacitive Feedback Trans-impedance Amplifier Optimization Using IPSO Algorithm
Hamid Niyazi Fakhralsadat Rastegari Majid Pourahmadi

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