List of Articles Power Delay Product

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  1 - A New 2-input CNTFET-Based XOR Cell With Ultra-Low Leakage Power For Low-Voltage and Low-Power Full Adders
  Amir Baghi Rahin Vahid Baghi Rahin
  The XOR gate is one of the basic building blocks in the Full Adder (FA) circuit, whose performance improvements can lead to improved Full Adder. For this purpose, in this paper, a new low voltage XOR cell based on Carbon Nanotube Field Effect Transistor (CNTFET) is prop More

  The XOR gate is one of the basic building blocks in the Full Adder (FA) circuit, whose performance improvements can lead to improved Full Adder. For this purpose, in this paper, a new low voltage XOR cell based on Carbon Nanotube Field Effect Transistor (CNTFET) is proposed. The main design goals for this new circuit are low power dissipation, low leakage current and full voltage swing at a low supply voltage (Vdd = 0.5 V). Several XOR circuits were completely simulated using HSPICE with 32nm CMOS and 32nm CNTFET technologies at a low supply voltage. The proposed XOR circuit is compared with the previously known circuits and its outstanding performance is shown. Simulations show that the new low voltage XOR has lower power dissipation, less leakage current and lower PDP than other XOR circuits, and is resistant to process variations. Based on the results obtained at Vdd=0.5 V ,frequency=250 MHz and Cload=3.5 fF, the proposed XOR shows propagation delay of 149.05 ps, power consumption of 716.72 pW, leakage power of 25.1 pW and PDP of 10.683x10-21 J. The proposed XOR can be used well in low voltage and low power Full Adder circuits. Manuscript profile
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  2 - Design and Simulation of 4 Transistors and 2 Memristors Memory with the Least Power and Power-Delay Product
  Keramat Karami Sayed Mohammad Ali Zanjani Mehdi Dolatshahi
  Memristor, as a fundamental element of SRAM and DRAM memories, can effectively reduce startup time and power consumption of the circuits. Non-volatility, high density of the final circuit, and reduction of power delay product (PDP) are some of the significant facts of m More

  Memristor, as a fundamental element of SRAM and DRAM memories, can effectively reduce startup time and power consumption of the circuits. Non-volatility, high density of the final circuit, and reduction of power delay product (PDP) are some of the significant facts of memristor circuits, which has led to the suggestion of a memory cell including and four transistors and two memristors (4T2M) in this paper. In order to simulate the proposed memory cell, the length of memristors has been selected 10 nm, and their on/off state resistors have been selected 250 Ω and 10 KΩ respectively. In addition, the proposed memory cell MOS transistors are simulated by the 32 nm CMOS PTM model. Simulation in the HSPICE software with 1V supply voltage and comparison with two conventional six-transistor (6T) and two transistors-two memory (2T2M) cells show that the use of memristors has made the proposed memory cell and 2T2M cell non-volatile. Moreover, the power consumption of the proposed circuit has decreased by 99.8% and 57.2%, compared to the previous two circuits respectively, and the power average delay product has also improved by 99.4% and 26.7%, respectively; however, the writing delay of this cell and 2T2M cell increased by 400% and 218% compared to 6T cell, respectively. Manuscript profile
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  3 - New CNFET- Based Full Adder cells for Low- Power and Low- Voltage Applications
  Mehdi Bagherizadeh Mohammad Eshghi
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