List of Articles Carbon Nanotube Field Effect Transistor

• Open Access Article
  • Abstract Page
  • Full-Text
  
  1 - A New 2-input CNTFET-Based XOR Cell With Ultra-Low Leakage Power For Low-Voltage and Low-Power Full Adders
  Amir Baghi Rahin Vahid Baghi Rahin
  The XOR gate is one of the basic building blocks in the Full Adder (FA) circuit, whose performance improvements can lead to improved Full Adder. For this purpose, in this paper, a new low voltage XOR cell based on Carbon Nanotube Field Effect Transistor (CNTFET) is prop More

  The XOR gate is one of the basic building blocks in the Full Adder (FA) circuit, whose performance improvements can lead to improved Full Adder. For this purpose, in this paper, a new low voltage XOR cell based on Carbon Nanotube Field Effect Transistor (CNTFET) is proposed. The main design goals for this new circuit are low power dissipation, low leakage current and full voltage swing at a low supply voltage (Vdd = 0.5 V). Several XOR circuits were completely simulated using HSPICE with 32nm CMOS and 32nm CNTFET technologies at a low supply voltage. The proposed XOR circuit is compared with the previously known circuits and its outstanding performance is shown. Simulations show that the new low voltage XOR has lower power dissipation, less leakage current and lower PDP than other XOR circuits, and is resistant to process variations. Based on the results obtained at Vdd=0.5 V ,frequency=250 MHz and Cload=3.5 fF, the proposed XOR shows propagation delay of 149.05 ps, power consumption of 716.72 pW, leakage power of 25.1 pW and PDP of 10.683x10-21 J. The proposed XOR can be used well in low voltage and low power Full Adder circuits. Manuscript profile
• Open Access Article
  • Abstract Page
  • Full-Text
  
  2 - Design and Simulation of a Bulk Driven Operational Transconductance Amplifier Based on CNTFET Technology
  Sayed Mohammad Ali Zanjani Mostafa Parvizi
  In this paper, a new two-stage OTA is proposed which meeting the needs of high gain, low power and low noise, and designed based on the gm/ID technique with bulk driven method. It is noteworthy that due to the limitations of CMOS technology, CNTFET technology used for t More

  In this paper, a new two-stage OTA is proposed which meeting the needs of high gain, low power and low noise, and designed based on the gm/ID technique with bulk driven method. It is noteworthy that due to the limitations of CMOS technology, CNTFET technology used for the circuit designs. Moreover, to improve the linearity of the circuit, triode transistors used in both stages of amplifiers. The simulation results of the proposed OTA are performed under 1V of supply voltage and 1pF of load capacitors in the HSPICE tool. According to the simulation results, the proposed circuit consumes less than 27 µW of power and offers a high gain of 98 dB. The CMRR and PSRR values of the proposed circuit are 121 dB and 152 dB, respectively. The input referred noise is 0.92 nV/√Hz and the slew rate of the proposed circuit is 111 V/µs, which shown the better figure of merit (FOM) in compression with the previous works.   Manuscript profile
• Open Access Article
  • Abstract Page
  • Full-Text
  
  3 - Design of a Low Power Temperature Sensor Based on Sub-Threshold Performance of Carbon Nanotube Transistors with an Inaccuracy of 1.5ºC for the range of -30 to 125ºC
  Sayed Mohammad Ali Zanjani Masoumeh Aalipour Mostafa Parvizi
  In this paper, a new temperature sensor based on the performance of carbon nanotube transistors in the subthreshold region is designed and simulated which leads to reduction of power consumption. Also, a differential amplifier is used in the output of the sensor. in ord More

  In this paper, a new temperature sensor based on the performance of carbon nanotube transistors in the subthreshold region is designed and simulated which leads to reduction of power consumption. Also, a differential amplifier is used in the output of the sensor. in order to keep the values of gain and common mode level voltage due to temperature changes, a method has been proposed that can compensate for these parameters variation due to temperature variation in the range of -30 ºC to +125 ºC. The proposed temperature sensor with its amplifier can be used as a system on the chip surface for temperature monitoring and control. The proposed temperature sensor in the CNTFET carbon nanotube field effect transistor technology with a supply voltage of 0.5 V in the sub-threshold area is simulated by HSPICE software with a 32nm CNT model. The simulation results show that at proposed circuits can measure the temperature in range of -30 ºC to +125 ºC linearly with a sensitivity of 1 mV/ ºC and consumes only 123 nW at room temperature. Also, the error measured at 125 ºC is about 2.5 mV, which means an error of 1.25 ºC at this temperature. Manuscript profile
• Open Access Article
  • Abstract Page
  • Full-Text
  
  4 - A Low Power Full Adder Cell based on Carbon Nanotube FET for Arithmetic Units
  Mokhtar Mohammadi Ghanatghestani Mehdi Bagherizadeh
  Manuscript profile