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Open Access Article
1 - Feature Extraction Framework for CBIR Systems based on Cyclic Transform Analysis & Spatial Information
Shahin Shafei Hamid Vahdati Tohid Sedghi Asghar CharminA novel framework of feature generation for Content based image retrieval (CBIR) is proposed. This system is realized on Cyclic transform Analysis (CTA). It introduces statistical descriptors in the signals frequency domain. Then the CT of data is computed by Semi super MoreA novel framework of feature generation for Content based image retrieval (CBIR) is proposed. This system is realized on Cyclic transform Analysis (CTA). It introduces statistical descriptors in the signals frequency domain. Then the CT of data is computed by Semi supervised algorithm (SSA) which is a simple & efficient algorithm. Presented Features are Norm-1 & energy CTA extracted from different sections of bi-frequency plane. This layout illustrate good characteristic in database. In addition, this manuscript illustrates a novel framework for generating textural and spatial information, and higher retrieval percentages. The textural features extracted with proposed CTA utilizing first & second moments among the image tiles is so effective in data processing. Spatial information is extracted utilizing decent field matrix (DFM). After that, moments are computed from DFM to get spatial features. The composition of the textural features and conjunction with the spatial information leads to a fantastic features matrix for retrieval. The experimental results on database guaranty the method efficiency on all classes of database with more than 10000 image. For measuring the distance of features a simple matching system based on Minkowski & Canberra distances is introduced. The results are compared with previous scholars and retrieval percentage is increased more than 10% in comparison with previous systems. Manuscript profile -
Open Access Article
2 - Design of a Low-Area, Low-Power and High-Speed Comparator in 65 nm FinFET Technology
Navid Sabzevari Mohammad Reza Yousefi S. Mohammadali ZanjaniIn the present study, a new low-power and high-speed comparator circuit is designed in 65 nm fin field-effect transistor (FinFET) technology. Moreover, by properly using the capabilities of FinFET technology, the number of transistors is reduced, and subsequently, a sma MoreIn the present study, a new low-power and high-speed comparator circuit is designed in 65 nm fin field-effect transistor (FinFET) technology. Moreover, by properly using the capabilities of FinFET technology, the number of transistors is reduced, and subsequently, a smaller area is occupied. Replacing MOSFET transistors with FinFETs reduces the delay and power consumption of the circuit, so the overall performance is improved. The first innovation of the proposed design is that to reduce the size and power consumption, two transistors were removed and the back gates of two transistors were cross-coupled. The second innovation is the connection of back gates to other suitable points of the circuit that increase the speed of comparison. In this study, a supply voltage of 0.8 V is applied to the circuit to show that the proposed modifications with FinFET reduce the delay to 272 ps and power consumption to 6.7 µW. Manuscript profile -
Open Access Article
3 - Optimal Load Shedding to Prevent Voltage Collapse Considering the Priority of Feeders and Buses
Somayeh Abdollahi Kakroudi Reza Ebrahimi Ahmad AhmadiToday, power systems are operated close to their stability limits for economic reasons. On the other hand, with the occurrence of outage, the stability of the system has a problem that there are various solutions to compensate. The last and safest way to control and mai MoreToday, power systems are operated close to their stability limits for economic reasons. On the other hand, with the occurrence of outage, the stability of the system has a problem that there are various solutions to compensate. The last and safest way to control and maintain system stability is load shedding. In this paper, under voltage load shedding is presented considering voltage dependent feeders load and also using the improved discrete particle swarm optimization algorithm (IDPSO). Since the load model is particular importance in the real load analysis, the decisions will be applied by considering voltage dependent load modeling. To ensure proper operation, the proposed method has been implemented using MATLAB software on the IEEE 30-bus test system by considering related constraints. For this purpose, two critical loads for the test system are considered and the results are examined. The results show that the proposed method provides the best location and amount of load shedding and indicates its effectiveness. Manuscript profile -
Open Access Article
4 - Circular Polarized Multi-Band Comb Antenna for Wireless and IoT Applications
Reza Khajeh Mohammad Lou Tohid aribi Tohid SedghiIn this research, a new multi-band microporous antenna with circular polarization is introduced for mobile and IoT applications. The applied frequency bands are covered simultaneously by the mentioned antenna, which are WLAN (2400 to 2484 MHz), WiMAX (IEEE 802.16e) 2500 MoreIn this research, a new multi-band microporous antenna with circular polarization is introduced for mobile and IoT applications. The applied frequency bands are covered simultaneously by the mentioned antenna, which are WLAN (2400 to 2484 MHz), WiMAX (IEEE 802.16e) 2500 to 2600 MHz, IoT (2400 to 2480 MHz with IEEE 802.11.ax standard, WLAN (5150 to 5825 MHz) which is called IEEE802.11ac standard. The antenna design process for accessing the desired frequency bands is performed step by step in the text of the article. Using the technique of facilitating the rotation of the current on the antenna, the excitation of two orthogonal modes is easily done and as a result, circular polarization is achieved. On the other hand, the circular polarization property is achieved in almost all the applied bands, which is considered as a significant advantage for this radiation system. The overall dimensions of the antenna are 0.8 × 34 ×23 mm3, which is fabricated on the FR4 substrate with a relative dielectric constant of 4.4 and a loss tangent of 0.024. In order to validate the design process, the structure is constructed and tested and measured. The extracted results show that the antenna has a directional radiation pattern and a good gain in the desired frequency bands. Manuscript profile -
Open Access Article
5 - The Circuit Design of the Receiving Part of the Portable Electroencephalogram System
Marzieh Moradi Mosoud DoustiIn recent years, many electroencephalogram (EEG) devices have become portable and wireless. Given the requirements for mobility, EEG instruments need to be smaller, lighter, and power-efficient with reduced noise and offset. An EEG signal is very weak and its amplitude MoreIn recent years, many electroencephalogram (EEG) devices have become portable and wireless. Given the requirements for mobility, EEG instruments need to be smaller, lighter, and power-efficient with reduced noise and offset. An EEG signal is very weak and its amplitude ranging is from 20 to 200 µV and its frequency ranges from 0.1 to 100 Hz. Besides, the skin-electrode interface creates a large DC offset voltage which can be in the order of ±300 mV. These two challenges can disturb the main signal and reduce the detection accuracy. At the input of amplification section of many EEG circuits, the chopping technique has been applied to convert DC input signals into AC signals. The main transconductance amplifier as EEG instrumentation amplifier (IA) in most of the previous works is the folded cascode amplifier. In this paper, we proposed a circuit which designed in 0.18 CMOS technology and its amplifier is a two-stage fully recycling chopper stabilized folded cascode amplifier that operates at low supply voltage and its input-referred noise is decreased by enhancing transconductance while it has a large slew rate, a high DC gain and an improved gain bandwidth. These features significantly decrease the noise and offset without a considerable increase in the power required by the circuit. In the post-layout simulation the amplifier achieves a midband gain of 60 dB and a -3dB bandwidth in the range of 0.1-210 Hz. the chip area with pads is 512×512 μm2. The adjustable LPF has a 100 Hz cut-off frequency. Manuscript profile -
Open Access Article
6 - Design of One Stage Class F High Power and High Frequency Power Amplifier with Two Parallel GaN Transistor for 2.5GHz Application
Bagher Zabihi Peiman Aliparast Naser NasirzadehIn this article, high frequency power amplifier is designed based on monolithic microwave integrated circuit (MMIC) technology. For this design the process of GaN transistors with high electron mobility has been used and its length gate technology is 150nm central frequ MoreIn this article, high frequency power amplifier is designed based on monolithic microwave integrated circuit (MMIC) technology. For this design the process of GaN transistors with high electron mobility has been used and its length gate technology is 150nm central frequency of the amplifier is 2.5GHz. the maximum gain of the amplifier is approximately equal to 12.76dB and is designed in one stage. At this frequency, the maximum output power of the amplifier is about 39.196 dBm in 30dBm input. In the maximum output power, PAE is about 41.25% that this is maximum amount of PAE .The final area of the circuit for embedding on the chip is 25.903mm by 19.346mm.the maximum values of AM/PM and AM/AM are 2.38deg/db and 1.66dB/dB respectively. For the 3-rd intermodulation distortion (IMD3) is about -20 dBc at the center of frequency. To design this amplifier, Loadpull analysis of ADS software was used to obtain the appropriate output power. Manuscript profile
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