Design of Low Power Single-Bit Full-Adder Cell Based on Pass-Transistor Logic

Subject Areas : Electronics Engineering

Mehdi Sayyaf ¹ (department of electrical engineering, bushehr branch, islamic azad university, bushehr, iran)
Abdolrasool Ghasemi ² (department of electrical engineering, bushehr branch, islamic azad university.bushehr, iran)
Roozbeh Hamzehyan ³ (department of electrical engineering, bushehr branch, islamic azad university, bushehr, iran)

Received: 2022-02-16 Accepted : 2022-07-14 Published : 2023-09-23

Keywords: Pass-transistor logic, Full adder, Minimum propagation delay, Low power,

Abstract :

In today's electronic and digital world, increasing demand for portable systems has led the electronics industry and chip design technology to reduce power consumption methods, and therefore power consumption has become an important criterion in this field. Also, increasing the speed of chips and reducing the propagation delay of circuits has always been an important goal of digital design engineers. Since the Adder element is one of the important elements in many digital systems, so today various Adders with different technologies and design approaches have been proposed, each of which has certain advantages and disadvantages. This paper presents a low-power single-bit full-adder cell design that is based on pass-transistor logic.This circuit is used in the arithmetic logic units of digital signal processors and also in several electronic and digital communication systems that operate within the frequency range of in 1GHz. The proposed cell exploits the pass transistor techniques and XOR-XOR structures to improve the design parameters namely power consumption, propagation delay, power–delay product, and the number of transistors. The proposed circuit is designed using 180nm CMOS technology and the simulation results show that for a supply voltage of 1.8V, the power consumption, delay, and power–delay product have been achieved as 83 W, 89ps, and 7fJ respectively.

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