Design and Implementation of a 16-bit Multi-Mode Delta-Sigma Digital-to-Analog Converter with Time-Interleaved Structure, Multi-Channel, and Compensation of Non-Idealities Based on FPGA

Abolfazl Roshanpanah ¹ ( PhD Student, Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran )
Pooya Torkzadeh ² ( Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran )
Khosrow Hajsadeghi ³ ( Associate Professor, Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran )
Massoud Dousti ⁴ ( Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran )

Submited date : 2024-03-11 Accepted date : 2024-04-20

Keywords: Delta-sigma modulator, Duty-cycle-error, Error-feedback, FPGA, Mismatch, Time-interleaved,

Abstract :

In this research, a 16-bit multi-mode second-order Delta-Sigma Modulator-Digital-to-Analog Converter (DSM-DAC) with a time-interleaved (TI) structure operating at a center frequency of 4 gigahertz (GHz) and a bandwidth of 20 megahertz (MHz) has been implemented using hardware description language (VHDL) on an FPGA platform. The proposed architecture utilizes a single clock frequency for generating radio frequency (RF) signals. The second-order Delta-Sigma modulator (DSM) is reconfigurable, offering three filter modes: low-pass (LP), band-pass (BP) at Fs/4, and high-pass (HP) for signal synthesis. To increase the sampling frequency (Fs), a TI structure with four channels is proposed, with each channel operating at Fs/4. Since the coefficients remain simple for all modes, multiplication operations can be achieved using a shift block. One significant challenge in designing such structures, especially in TI mode, is cycle-to-cycle duty cycle error (DCE) impact. In this study, a novel solution is proposed to overcome the DCE effect by adjusting the filter circuit and unilaterally narrowing the signal passband without adding extra hardware complexity. This approach significantly enhances the Signal-to-Noise and Distortion Ratio (SNDR) and Spurious-Free Dynamic Range (SFDR) of the DSM output, even for the BP mode. Another challenge is the mismatch error in DAC cells. In this research, this error is simulated and compensated using two methods: Weighted Data Averaging (DWA) and Sorted Dynamic Element Matching (SDEM). Simulation results in ISE demonstrate that the SNDR values for LP, BP, and HP modes are 106.10, 105.65, and 104.95 dB, respectively.

highlight:

• A 16-bit multi-mode digital-to-analog converter with a time-interleaved structure at a frequency of 4 GHz.
• Only one clock frequency is used to generate the radio frequency signal.
• There are simple coefficients for all cases, the multiplication operation can be performed using a shifter block.
• Two dominant errors in TI-DSM-DACs (mismatch and duty-cycle-error (DCE)) have been compensated.
• A new method is proposed to remove the effect of signal image in BP mode, instead of using complex circuits.

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