TY  - JOUR
AU  - Torkzadeh, Pooya
AU  - Roshanpanah, Abolfazl
AU  - Hajsadeghi, Khosrow
AU  - Dousti, Massoud
TI  - Design and Implementation of a 16-bit Multi-Mode Delta-Sigma Digital-to-Analog Converter with Time-Interleaved Structure, Multi-Channel, and Compensation of Non-Idealities Based on FPGA
JO  - Journal of Southern Communication Engineering
VL  - 14
IS  - 54
SP  - 93
EP  - 117
PY  - 2025
DO  - 10.30495/jce.2025.1993480.1330
ER  -