طراحی کارآمد تقسیم کننده غیربازیابی برگشت پذیر با قابلیت حفظ توازن
الموضوعات :
محمد طالبی
1
,
محمد مصلح
2
,
محسن چکین
3
1 - دانشکده فنی و مهندسی، گروه کامپیوتر، دانشگاه آزاد اسلامی واحد دزفول، دزفول، ایران
2 - دانشکده فنی و مهندسی، گروه کامپیوتر، دانشگاه آزاد اسلامی واحددزفول، دزفول، ایران
3 - دانشکده فنی و مهندسی، گروه کامپیوتر، دانشگاه آزاد اسلامی واحد دزفول، دزفول، ایران
الکلمات المفتاحية: تقسیم کننده, الگوریتم با روش غیربازیابی, محاسبات کوانتومی, منطق برگشت پذیر, مدار برگشت پذیر با قابلیت حفظ توازن ,
ملخص المقالة :
یکی از چالش¬های اساسی در مدارات مجتمع پرتراکم، اتلاف توان مصرفی است که به واسطه وجود ترانزیستورها در مدارات ایجاد می¬شود و موجب می¬گردد دمای مدار افزایش یابد. طراحی مدارات دیجیتال به شیوه برگشت‌پذیر می¬تواند به عنوان یکی از رویکردهای کارآمد برای رفع این چالش به کار گرفته شود. علاوه بر این، طراحی مدارات برگشت‌پذیر با قابلیت حفظ توازن می¬تواند در تشخیص اشکالات در مدارات بسیار مؤثر باشد. تقسیم‌کننده¬ها به عنوان یکی از مدارات پرکاربرد در سیستم¬های محاسباتی دیجیتال مورد استفاده قرار می¬گیرند. مدارات تقسیم¬کننده متشکل از واحد¬های پایه¬ای جمع¬کننده، مالتی¬پلکسر و دو مدار ترتیبی ثبات و ثبات شیفت به چپ با قابلیت بار شدن موازی هستند. این مقاله یک طراحی جدید و کارآمد از تقسیم-کننده غیربازیابی برگشت¬پذیر با قابلیت حفظ توازن ارائه می¬کند. برای این منظور در ابتدا یک نگهدارنده حالت نوع D برگشت‌پذیر با قابلیت حفظ توازن پیشنهاد شده است. سپس یک ثبات n بیتی برگشت¬پذیر با قابلیت حفظ توازن با استفاده از نگهدارنده حالت برگشت¬پذیر پیشنهادی ارائه گردیده است. در ادامه یک شیفت ثبات n+1 بیتی برگشت‌پذیر با ¬قابلیت حفظ توازن با استفاده از نگهدارنده پیشنهادی و سایر دروازه‌های برگشت‌پذیر پیشنهاد شده است. در نهایت تقسیم¬کننده برگشت¬پذیر n بیتی با قابلیت حفظ توازن بر اساس الگوریتم غیربازیابی توسعه یافته است. نتایج حاصل از مقایسه¬ها نشان می¬دهند مدار پیشنهادی از لحاظ معیارهای ارزیابی مدارات برگشت¬پذیر همچون هزینه کوانتومی، تعداد ورودی¬های ثابت و تعداد خروجی-های زائد در مقایسه با کارهای پیشین برتری دارند.
Proposing a reversible D-latch memory with parity preserving ability
Introducing a reversible register with parity preserving ability
Providing a parity preserving reversible left-shift register with parallel load capability (PIPO)
Development of an efficient parity preserving reversible non-restoring divider using the proposed circuits
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