• فهرست مقالات fault tolerance

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        1 - Improving the palbimm scheduling algorithm for fault tolerance in cloud computing
        Minoo Soltanshahi
        Cloud computing is the latest technology that involves distributed computation over the Internet. It meets the needs of users through sharing resources and using virtual technology. The workflow user applications refer to a set of tasks to be processed within the cloud چکیده کامل
        Cloud computing is the latest technology that involves distributed computation over the Internet. It meets the needs of users through sharing resources and using virtual technology. The workflow user applications refer to a set of tasks to be processed within the cloud environment. Scheduling algorithms have a lot to do with the efficiency of cloud computing environments through selection of suitable resources and assignment of workflows to them. Given the factors affecting their efficiency, these algorithms try to use resources optimally and increase the efficiency of this environment. The palbimm algorithm provides a scheduling method that meets the majority of the requirements of this environment and its users. In this article, we improved the efficiency of the algorithm by adding fault tolerance capability to it. Since this capability is used in parallel with task scheduling, it has no negative impact on the makespan. This is supported by simulation results in CloudSim environment. پرونده مقاله
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        2 - CAFT: Cost-aware and Fault-tolerant routing algorithm in 2D mesh Network-on-Chip
        Akram Reza Parisa Jolani Midia Reshadi
        By increasing, the complexity of chips and the need to integrating more components into a chip has made network on- chip known as an important infrastructure for network communications on the system, and is a good alternative to traditional ways and using the bus. By in چکیده کامل
        By increasing, the complexity of chips and the need to integrating more components into a chip has made network on- chip known as an important infrastructure for network communications on the system, and is a good alternative to traditional ways and using the bus. By increasing the density of chips, the possibility of failure in the chip network increases and providing correction and fault tolerance methods is one of the principles of today's chip design. Faults may have undesirable effects on the correct system operation and system performance. In this paper the communication infrastructure failure has been considered as same as link and router failure and the fault tolerance low cost routing algorithm has been suggested base on local fault information By using quad neighbor fault information to avoid back tracking in routing in order to select possible minimal path to destination. In this article, we have suggested cost aware fault tolerance (CAFT) routing algorithm. Our contribution in this algorithm is minimum local fault information, minimum routing decision overhead by implementing routing logic base and determining shortest possible path. For deadlock freedom using an additional virtual channel along Y dimension and prohibiting certain routing turns. In order to evaluate the performance of our routing, we compared it with other fault tolerant routing in terms of average packet latency, throughput and power. پرونده مقاله
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        3 - الگوریتم تحمل پذیری خطا و انتقال قابل اعتماد داده در بستر اینترنت اشیاء
        محسن  مظفری وانانی پویا خسرویان دهکردی
        محدودیت‌های اینترنت اشیا (IoT)، باعث شده تا رخداد خطا در این شبکه‌ها امری انکارناپذیر بوده و تضمین تحمل‌پذیری خطا به جهت صحت عملکرد شبکه الزامی باشد. اگرچه هر یک از این پژوهش‌ها با کار کردن بر روی جوانب مختلف این حوزه به نوبه خود در بهبود تحمل‌پذیری خطا مؤثر بوده‌اند. ا چکیده کامل
        محدودیت‌های اینترنت اشیا (IoT)، باعث شده تا رخداد خطا در این شبکه‌ها امری انکارناپذیر بوده و تضمین تحمل‌پذیری خطا به جهت صحت عملکرد شبکه الزامی باشد. اگرچه هر یک از این پژوهش‌ها با کار کردن بر روی جوانب مختلف این حوزه به نوبه خود در بهبود تحمل‌پذیری خطا مؤثر بوده‌اند. اما مطالعات حاکی از آن است که روش‌های گذشته در حفظ پیوستگی و تضمین صحت مبادله داده‌ها، به ویژه در هنگام رخداد خطا ناکارآمدند. وجود این مسئله صراحتاً به ضرورت ارائه روش‌هایی جدید با قابلیت تضمین صحت مبادله داده‌ها اشاره داشته، تا در شرایط مختلف پایداری عملکرد شبکه تضمین گردد. جهت تحقق این مهم، در اين مقاله روش FTRTA بر مبنای توسعه پروتکل RPL و بهره‌وری از تکنیک توزیع داده معرفی شده است. تکنیک‌های توزیع از جمله تکنیک‌های مؤثری بوده که علاوه بر تحمل‌پذیری خطا در بهبود توازن بار ترافیکی شبکه نیز می‌توانند مؤثر باشند. FTRTA به جهت پیشبرد عملکرد خود شامل سه مرحله کلی بوده، به‌طوری که در مرحله نخست همروند با فرایند ارسال DIOها وضعیت گره‌های شبکه ارزیابی شده، در گام دوم گراف ارتباطی شبکه تشکیل شده و در گام مخابره داده‌ها بر حسب تکنیک توزیع داده و با هدف تضمین تحمل‌پذیری خطا انجام می‌شود. نتايج شبيه‌سازی با استفاده از نرم‌افزار Cooja حاکی از کارایی بالای FTRTA در حفظ پیوستگی و تضمین صحت مبادله داده‌ها، و بهبود معیارهايی همچون دریافت‌های موفق و گذردهی شبکه، در مقایسه با پژوهش‌های مشابه است. پرونده مقاله
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        4 - Fault Tolerant Design of QCA Binary Wire
        Mojdeh Mahdavi Mohammad Amin Amiri
        Dependability of a circuit is among the most important issues in the design process and reliability concerns are associated with the digital system design. A fault tolerant system should have the ability to detect, locate and correct the error and recover the system to چکیده کامل
        Dependability of a circuit is among the most important issues in the design process and reliability concerns are associated with the digital system design. A fault tolerant system should have the ability to detect, locate and correct the error and recover the system to normal operational conditions. It is more important to use fault tolerant gates in nano scale digital circuits because by decreasing the device dimensions the influence of external factors and therefore the probability of fault occurrence will increase. Since the binary wire is an essential part of digital systems and especially QCA (Quantum Cellular Automata) circuits, a redundancy based fault tolerant technique is presented in this paper to improve the fault tolerance of this part. The efficiency of this method is evaluated by MATLAB software. Results show that the fault tolerance of binary wire will significantly increase by using the proposed method. The hardware redundancy of this method is about 100% which is much less than TMR (Triple Module Redundancy) methods by more than 200% redundancy. پرونده مقاله
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        5 - Fault Tolerance and Interference Aware Topology Control in Wireless Sensor Networks using NSGA-II
        Nahid Sarbandi Farahani Asad Vakili
        Research on topology control protocols in wireless sensor networks has often been designed with the goal of creating a dynamic topology and extensibility. The present study focuses on finding high quality paths, instead of minimizing the number of hops that can cause re چکیده کامل
        Research on topology control protocols in wireless sensor networks has often been designed with the goal of creating a dynamic topology and extensibility. The present study focuses on finding high quality paths, instead of minimizing the number of hops that can cause reduction of the received signal strength and maximizing the rate of loss. The purpose of this research is to create a topology control that focuses on reducing the fault and minimizing interference simultaneously. For this purpose, the fault rate and the degree of interference minimizing functions are modeled by using a two-objective genetic algorithm. Since the genetic algorithm is a revelation algorithm, the proposed method is compared in terms of convergence with similar algorithms. The obtained graphs show that the proposed algorithm has a good degree of convergence compared to similar models. The "runtime", "memory consumption" and "energy required to transmit the statement" are the variables used to compare with similar algorithms. By observing the obtained graphs, the proposed algorithm compared to similar methods, reduces the time needed for topology control and also it lowers the energy consumption, but is not able to reduce memory consumption for more packages. The main reason for conducting the test is the comparison of the quality of the routes created, which were executed in 20 different requests with the number of routes 5, 10 and 20. The quality of the routes produced by the proposed method has a 1% improvement over the SMG method and a 3% compared to the PSO method according to the route quality criteria. پرونده مقاله
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        6 - Improving the Mean Time to Failure of the System with the New Architecture of the Main Node with the Replacement Node of Industrial Wireless Sensor Networks for Monitoring and Control using Markov Model
        Ahmadreza Zamani Mohammad Ali Pourmina Ramin Shaghaghi Kandovan
        10.30486/mjtd.2022.695924
        Industrial and physical site information is sent to the monitoring center by sensors in wireless sensor networks so that they can easily control the process of a company in order to improve the optimal performance of the system until the failure occurs to monitor and co چکیده کامل
        Industrial and physical site information is sent to the monitoring center by sensors in wireless sensor networks so that they can easily control the process of a company in order to improve the optimal performance of the system until the failure occurs to monitor and control in wireless sensor networks. Sensors are exposed to a wide range of failures, possible hardware and software problems in normal conditions, extreme weather conditions or other conditions caused by harsh physical environment in the field of sensors. Therefore, there is a possibility of unpredictable failure for all types of sensors and with Industrial process monitoring, preventive status monitoring, prevented error and fault and failures. The focus of this article is to present a new architecture in improving the correct performance of the system, the replacement rate of more damaged nodes and timely replacement, at the time of the starting point of the failure, the main sensor with spare ones or healthy sensors with faulty ones. The proposed network structure is such that the spare node is placed in parallel with the main node; this method makes it possible for the spare node to be replaced in case of failure of the main node, and the failed node can be quickly repaired and put in a standby mode. Our proposed model is analyzed in terms of the average time of correct system operation until failure known as mean time to failure. In this article is presented and studied and evaluated, a new architecture to improve network performance against failure using Markov model and state probability, and mean failure rate for node fault tolerance, before failure with timely replacement in wireless sensor network. In the proposed architecture, the results show a better improvement of the system's correct performance in order to reduce the adverse effects of errors and failures and improve fault tolerance. The simulation results show that the advantage of using this method reduces the adverse effects of errors and failures and improves the optimal performance of the system in the industrial site. پرونده مقاله
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        7 - افزودن قابلیت تحمل پذیری خطا به متدولوژی MaSE برای سیستم های چند عامله
        محمد حسین داورپور
        برنامه های کاربردی زیادی امروزه بر مبنای مفهوم سیستمهای چند عامله شکل گرفته اند و نیازمند این هستند که به طور پیوسته و بی وقفه کار کنند. سیستمهای چند عامله نیز از بروز خطا مصون نیستند. به همین دلیل لازم است که تحمل پذیری خطا به عنوان یک نیاز غیر وظیفه مندی تا حد امکان ب چکیده کامل
        برنامه های کاربردی زیادی امروزه بر مبنای مفهوم سیستمهای چند عامله شکل گرفته اند و نیازمند این هستند که به طور پیوسته و بی وقفه کار کنند. سیستمهای چند عامله نیز از بروز خطا مصون نیستند. به همین دلیل لازم است که تحمل پذیری خطا به عنوان یک نیاز غیر وظیفه مندی تا حد امکان برای آنها تامین گردد. روش های ارائه شده برای تحمل پذیری خطا تا به حال، بیشتر مبتنی بر تکثیر عامل ها بوده اند که خود باعث پیچیدگی بیش از حد سیستم می گردد. از همین رو در این مقاله سعی شده است تا با تکیه بر روش تکثیر وظیفه ها به جای فقط تکثیر عامل ها و اعمال این روش در متدولوژی MaSE، با توجه به مطلوبیت و کاربرد زیاد این متدولوژی در تحلیل و طراحی سیستمهای چند عامله، به یک طراحی کارا با قابلیت تحمل پذیری خطا برای سیستمهای چند عامله دست یابیم. پرونده مقاله
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        8 - An Evolutionary Method for Improving the Reliability of Safetycritical Robots against Soft Errors
        Mahnaz Mohammadzadeh Bahman Arasteh
        Nowadays, Robots account for most part of our lives in such a way that it is impossible for usto do many of affairs without them. Increasingly, the application of robots is developing fastand their functions become more sensitive and complex. One of the important requir چکیده کامل
        Nowadays, Robots account for most part of our lives in such a way that it is impossible for usto do many of affairs without them. Increasingly, the application of robots is developing fastand their functions become more sensitive and complex. One of the important requirements ofRobot use is a reliable software operation. For enhancement of reliability, it is a necessity todesign the fault tolerance system. In this paper, we will present a genetic algorithm andlearning automata with high reliability to evaluate the software designed into the robotagainst soft-error with minimum performance over-head. This method relies on experiment;hence, we use the program sets as criteria in evaluation stages. Indeed, we have used the errorinjection method in the execution of experimental processes. Relevant data, regardingprogram execution behavior were collected and then analyzed. To evaluate the behavior ofprogram, errors entered using the simple scalar simulation software. پرونده مقاله
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        9 - طراحی مدارهای محاسباتی با استفاده از دروازه اکثریت 7 ورودی جدید در آتوماتای سلولی کوانتومی
        فرزانه جهانشاهی جواران سمیه جعفرعلی جاسبی حسین خادم الحسینی راضیه فرازکیش
        آتوماتای سلولی کوانتومی (QCA) نوعی فن آوری محاسباتی است که جهت ساخت مدارهایی در ابعاد نانو به کار برده می‌شود. با کاهش ابعاد قطعات، حساسیت مدار بیشتر شده و مدارهای کوانتومی نسبت به وقوع عیوب و تشعشعات محیط آسیب پذیرتر هستند. دو دروازه پایه در این فن آوری دروازه معکوس کن چکیده کامل
        آتوماتای سلولی کوانتومی (QCA) نوعی فن آوری محاسباتی است که جهت ساخت مدارهایی در ابعاد نانو به کار برده می‌شود. با کاهش ابعاد قطعات، حساسیت مدار بیشتر شده و مدارهای کوانتومی نسبت به وقوع عیوب و تشعشعات محیط آسیب پذیرتر هستند. دو دروازه پایه در این فن آوری دروازه معکوس کننده و دروازه اکثریت هستند که بیشتر مدارها بر پایه این دو ساخته می شوند. در این مقاله دروازه‌ اکثریت هفت ورودی در QCA طراحی می شود، به گونه ای که حداقل سربار به مدار تحمیل شود. استفاده از دروازه اکثریت با ورودی های بیشتر باعث کاهش تعداد سلول ها، تاخیر و پیچیدگی در مدار QCA می شود. هرچند شاید ضرورت استفاده از دروازه هفت ورودی هنوز چندان احساس نمی شود. گیت پیشنهادی در این مقاله با 19سلول کوانتومی در فضای اشغالی 24564 نانومتر مربع در یک لایه و با یک فاز کلاک طراحی شده است. سپس تعدادی از دروازه های منطقی از جمله دروازه های منطقی "و" و"یا" چهار ورودی، دروازه "نقیض یای انحصاری" و "یای انحصاری" دو ورودی، دروازه"یای انحصاری" سه ورودی و تمام جمع کننده چند بیتی را با استفاده از دروازه هفت ورودی پیشنهادی طراحی و پیاده سازی می شود. جمع کننده پیشنهادی با دروازه اکثریت هفت ورودی و یک دروازه اکثریت سه ورودی تحمل پذیر اشکال، طراحی شده است. پس می توان گفت که جمع کننده طراحی شده تا حدودی تحمل پذیر اشکال است یعنی در برابر خطاهایی که در این فن آوری رخ می دهد تا حدودی تحمل پذیر است. سپس از نرم افزار QCAPro برای تجزیه و تحلیل توان مصرفی دروازه پیشنهادی استفاده شده و در ادامه عملکرد مدار با استفاده از نرم افزار شبیه ساز آتوماتای سلولی کوانتومی QCADesigner 2.0.3 مورد ارزیابی قرار گرفته است. پرونده مقاله
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        10 - ارائه روشی سیستماتیک برای تحلیل حساسیت سیستم‌های تحمل‌پذیر خطا در معماری افزونگی چند ماجولی
        کوروش اصلان صفت غلامرضا لطیف شبگاهی
        درخت عیب یک دیاگرام سلسله مراتبی است که راههای مختلف ترکیب اجزای معیوب یک سیستم را که منجر به وقوع عیب نامطلوب مشخص در آن می‌شوند به تصویر می‌کشد. این دیاگرام در فازهای طراحی و بهره‌برداری سیستم‌های صنعتی به کار رفته و به طراحان امکان ارزیابی ویژگی‌هایی نظیر قابلیت اطمی چکیده کامل
        درخت عیب یک دیاگرام سلسله مراتبی است که راههای مختلف ترکیب اجزای معیوب یک سیستم را که منجر به وقوع عیب نامطلوب مشخص در آن می‌شوند به تصویر می‌کشد. این دیاگرام در فازهای طراحی و بهره‌برداری سیستم‌های صنعتی به کار رفته و به طراحان امکان ارزیابی ویژگی‌هایی نظیر قابلیت اطمینان، میانگین زمان تا خرابی و حساسیت را عرضه می‌کند. علاوه بر موارد مذکور از درخت عیب برای پیدا کردن گلوگاه‌های خرابی و تعیین نقاط ضعف طراحی استفاده می‌کنند. علیرغم کاربردهای وسیع آن در ارزیابی قابلیت اطمینان سیستمها، از درخت عیب کمتر برای محاسبه حساسیت استفاده شده است. در دهه اخیر تحقیقات محدودی در این زمینه صورت گرفته‌ است، اما این روش‌ها برای سیستم‌های بزرگ کارایی نداشته و نظام‌مند نیستند. مقاله حاضر به ارائه روشی سیستماتیک برای ارزیابی حساسیت سیستم‌های تحمل‌پذیر خطا از روی درخت عیب آن می‌پردازد. سپس روش فوق را برای محاسبه حساسیت معماری NMR که یکی از ساختارهای متعارف تحمل‌پذیری‌خطا که جهت افزایش قابلیت اطمینان، ایمنی و دردسترس‌پذیری سیستم ها در صنعت است، به کار گرفته و به ارائه فرمولی جامع و پارامتری برای محاسبه حساسیت این ساختار می‌پردازد. روش ارائه شده می‌تواند کمک شایانی به مهندسان طراح و بهره‌بردار سیستم‌های مطمئن برای محاسبه سیستماتیک و سریع حساسیت از روی درخت عیب آنها بنماید پرونده مقاله
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        11 - Design and Analysis of a Fault Tolerant 3-Input Majority Gate in Quantum-dot Cellular Automata
        Somayyeh Jafarali Jassbi Farzaneh Jahanshahi Javaran Hossein Khademolhosseini Amir Sabbagh Molahosseini
        QCA is a kind of computational technology used for developing circuits in Nano sizes. Decreasing the dimensions of pieces has led to the increase of circuit sensibility and quantum circuits are more vulnerable to defects and radiations of the environment. Majority gate چکیده کامل
        QCA is a kind of computational technology used for developing circuits in Nano sizes. Decreasing the dimensions of pieces has led to the increase of circuit sensibility and quantum circuits are more vulnerable to defects and radiations of the environment. Majority gate and NOT gate (inverter) are the two basic gates in QCA technology based on which almost all circuits are made. So far, a limited number of fault-tolerant majority gates have been presented and research in this particular field seems appropriate. In this research we intend to provide a comprehensive design of 3-input majority gate in quantum cellular automata for all possible faults: misalignment, missing, dislocation, and redundancy so that low overhead is added to circuit. The gate is made up of both 90-degree and 45-degree cells. The results of this study indicate that our proposed 3-input majority gate is more fault-tolerant to the defects compared to the formerly presented one. پرونده مقاله
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        12 - Proposing a Novel Algorithm for Fault-Tolerant Relay Node Placement in Wireless Sensor Networks
        Hamid Barati Mohsen Sedighi Ali Movaghar Iman Attarzadeh
        Wireless sensor networks are composed of hundreds or thousands of small nodes called sensor that work together and are associated with a specific task or tasks to do. Each of these nodes includes sensor, processor, communication components, a small memory and a source o چکیده کامل
        Wireless sensor networks are composed of hundreds or thousands of small nodes called sensor that work together and are associated with a specific task or tasks to do. Each of these nodes includes sensor, processor, communication components, a small memory and a source of energy.It is expected that wireless sensor networks will be used widely in many applications in near future. Scalability and lifetime extension in wireless sensor networks are critical issues in designing and implementing a wireless Sensor Network (WSN).Relay Nodes (RNs) in WSN are nodes with higher useful power and radius, which considered as head of network. RNs are able to disseminate data in a higher level, network clusters, and network regions. In this paper, a novel algorithm is proposed to cover all sensor nodes with the least possible RNs. The number of RNs can be calculated through a proposed mathematical function which has the maximum rate of detection. The proposed approach shows high capability for fault tolerance in WSN when compared to other algorithms. پرونده مقاله
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        13 - Presenting a Fault Tolerant Mechanism for Buffering Fault in Network on Chips
        Sadeq Lotfi Ali Afzali-kusha Marzie Saffari
        As technology scales deep into the nanometer regime, on-chip communication becomes more susceptible to transient noise sources, such as crosstalk, external radiation, and spurious voltage spikes. The Network on chip s modularity and reusability has brought about the use چکیده کامل
        As technology scales deep into the nanometer regime, on-chip communication becomes more susceptible to transient noise sources, such as crosstalk, external radiation, and spurious voltage spikes. The Network on chip s modularity and reusability has brought about the use of error control methods to address transient errors in Network on chip links.In this work, we design a fault tolerance router with efficient area and power dissipated. Actually, we exploit the free virtual channel to store the redundant data. Virtual channel is used for deadlock avoidance it can be implement as 2, 4 or 8 channel. The almost time we can find a free channel that we can use in fault tolerance mechanism. We describe the proposed architecture with VHDL and implemented with synopsis compiler design. We use analytical model to evaluate the fault tolerance. The result shows that we improve the dynamic power dissipation, area, and reliability. پرونده مقاله
      • دسترسی آزاد مقاله

        14 - New Fault-Tolerant Majority Gate for Quantum Dots Cellular Automata
        Razieh Farazkish
        In the high voltage (HV) electrical power systems, different materials are used as the role of insulation to protect the incipient failure inside the HV power equipments. One of the common phenomenas in insulations is Partial Discharge (PD). Because of the high voltage چکیده کامل
        In the high voltage (HV) electrical power systems, different materials are used as the role of insulation to protect the incipient failure inside the HV power equipments. One of the common phenomenas in insulations is Partial Discharge (PD). Because of the high voltage stress, the weak section inside the insulator causes the partial discharge (PD), which is known as a local electrical breakdown. The maximum amplitude of PD could accelerate the destruction process of insulation material. Also, during practical applications in the power systems, voltages with different levels are used or created suddenly. Therefore, it is necessary to analyze the effect of voltage characteristics on the PD. In this paper, the effect of DC, AC and impulse voltage on the maximum amplitude of PD are studied within the MATLAB Simulink platform. Finally, to show the effect of each voltage level on the PD, results are compared with each other in the single and multi cavity situations. The test materials for this research are epoxy resin and oil-impregnated paper. Also, this paper provides a comparison between two different insulation materials. پرونده مقاله
      • دسترسی آزاد مقاله

        15 - New Approach to Design and Implementation XOR Gate in QCA Technology
        Somayeh Aghababaei Samira Sayedsalehi
        Quantum-dot cellular automata (QCA) is a novel technology that encodes binary information with state of electrons instead of voltage levels. QCA computations offer ultra-low power consumption, high speed and density construction. Majority voter and inverter are the most چکیده کامل
        Quantum-dot cellular automata (QCA) is a novel technology that encodes binary information with state of electrons instead of voltage levels. QCA computations offer ultra-low power consumption, high speed and density construction. Majority voter and inverter are the most important gates in this technology and other gates and circuits can be implemented with them. In this paper, we design a novel fault tolerant two-input XOR gate. That is implemented in single layer without any wire crossing. One of the fundamental logical gates in digital circuits is exclusive-OR (XOR). Many circuits can be implemented with XOR such as full adder, comparator and so on. We design this gate according to Boolean expressions with one three-input majority gate and one five-input majority gate. The proposed design has significant improvement in terms of area, complexity, latency, and cell count in comparison to the previous designs. This component is suitable for designing fault tolerant QCA circuits. We simulate our design in QCA Designer and QCA Pro and achieved results are presented in this paper. پرونده مقاله
      • دسترسی آزاد مقاله

        16 - Fault-Tolerant Techniques for Quantum-dot Cellular Automata Circuits and Systems
        Razieh Farazkish Mani Zarei
        This paper explains fault tolerance techniques for Quantum-dot cellular automata which offer remarkable robustness to implement QCA arithmetic circuits. It begins with a study of QCA based design. A classification for fault types is presented and some fault tolerance te چکیده کامل
        This paper explains fault tolerance techniques for Quantum-dot cellular automata which offer remarkable robustness to implement QCA arithmetic circuits. It begins with a study of QCA based design. A classification for fault types is presented and some fault tolerance techniques are examined and their relevance for QCA circuits is evaluated. Finally, it is concluded that a combination of two or more hardware redundancy techniques is needed for tolerating faults in QCA circuits and systems. The proper functionality of the presented design is checked by computer simulations using the QCADesigner tool. Simulation results confirm our claims and their usefulness in designing robust digital circuits. پرونده مقاله

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