فهرست مقالات Heterojunction

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  1 - Synthesis of n-type and p-type CuInS2 thin films via simple SILAR method
  hossien Alehdaghi Mohammad Zirak
  Among various CuInS2-rerlated heterojunctions, it is expected that CIS-based p−n junctions are high-performance photo-active electrodes. Herein, both n-type and p-type CuInS2 thin films were synthesized via facile successive ion layer adsorption and reaction (SILA چکیده کامل

  Among various CuInS2-rerlated heterojunctions, it is expected that CIS-based p−n junctions are high-performance photo-active electrodes. Herein, both n-type and p-type CuInS2 thin films were synthesized via facile successive ion layer adsorption and reaction (SILAR) method, using aqueous (A-CIS) and mathanolic (M-CIS) SILAR solutions, respectively. Based on UV-visible transmission spectra, M-CIS thin films were more transparent with larger band gap energy (1.6 eV) than A-CIS thin films (1.5 eV). The A1-mode Raman peak of M-CIS thin film was located at 293 cm-1 which has a red shift of 5 cm-1 as compared to A-CIS one, indicating that M-CIS has smaller CuInS2 nanoparticles. The Mott-Schottky plots revealed that A-CIS is an n-type semiconductor, while M-CIS thin films have p-type semiconducting behavior, which is due to different Cu/In ratio in these thin films. The obtained results can be very useful to prepared CIS-based p-n junctions toward high performance solar-based devices. پرونده مقاله
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  2 - Performance Analysis of InAs/AlGaSb Heterojunction Electron-Hole Bilayer Tunnel Field Effect Transistor for Low-Power High-Speed Digital Computing
  Zahra Ahangari
  10.30495/ijsee.2023.1988303.1268
  In this paper, a novel device, namely heterojunction electron-hole bilayer tunnel field effect transistor (HJ-EHBTFET), is proposed which outperforms conventional tunnel field effect transistor (TFET) in terms of electrical performance. The use of lattice matched InAs/A چکیده کامل

  In this paper, a novel device, namely heterojunction electron-hole bilayer tunnel field effect transistor (HJ-EHBTFET), is proposed which outperforms conventional tunnel field effect transistor (TFET) in terms of electrical performance. The use of lattice matched InAs/Al0.6Ga0.4Sb material combination results in a broken band gap configuration, making it highly suitable for high speed ultra-low applications, as it requires smaller gate bias for the onset of tunneling. The impact of critical design parameters on the device performance is comprehensively investigated. The proposed device utilizes electrical doping instead of physical doping for the creation of tunneling junction, which effectively addresses the problem of low solubility of dopants in heavily doped III-V materials. The top gate and bottom gate workfunction are critical design parameters that effectively modulated the electrically induced charges at the tunneling junction and consequently, affect the tunneling rate. In order to obtain the lowest possible transition voltage for the onset of tunneling, a variation matrix of threshold voltage variation is computed as a function of gate electrode workfunction. Through this process, a step-like behavior from off-state to on-state has been achieved, with a subthreshold swing of 3 mV/dec and on/off current ratio of 5.8×1012, thereby paving the way for the design of low-power high-speed digital computing systems. پرونده مقاله