طراحی و شبیه‌سازی مدارهای جمع‌کننده کم‌مصرف با استفاده از گیت MGDI در فناوری QCA
محورهای موضوعی : مهندسی برق و کامپیوتر
حمیدرضا صدر ارحامی
1
,
سیدمحمدعلی زنجانی
2
,
مهدی دولتشاهی
3
,
بهرنگ برکتین
4
1 - دانشکده مهندسی کامپیوتر، واحد نجفآباد، دانشگاه آزاد اسلامی، نجفآباد، ایران
2 - دانشکده مهندسي برق، واحد نجفآباد، دانشگاه آزاد اسلامی، نجفآباد، ايران
3 - دانشکده مهندسي برق، واحد نجفآباد، دانشگاه آزاد اسلامی، نجفآباد، ايران
4 - دانشکده مهندسی کامپیوتر، واحد نجفآباد، دانشگاه آزاد اسلامی، نجفآباد، ایران
کلید واژه: آتاماتای سلولی کوانتومی, سامانه‌های کم‌مصرف, تکنیک انتشار پایانه ورودی, تمام جمع‌کننده,
چکیده مقاله :
با طراحی مدارها در ابعاد نانو و مشاهده مشکلات فناوری CMOS، طراحان به دنبال جایگزین¬های مناسب برای این فناوری هستند. آتاماتای سلولی کوانتومی QCA، یکی از این فناوری‌های پیشنهادی است که باتوجه‌به سرعت بالا و توان مصرفی پایین، توجه محققان را به خود جلب کرده است. از طرفی، روش ورودی انتشار گیت GDI یک روش بهبود توان و مساحت اشغالی است که با استفاده از تعداد ترانزیستور کمتر، منجر به‌سرعت بیشتر، اتلاف توان کمتر و كاهش پيچيدگي در توابع بولي شده است. همچنین جمع‌کننده به‌عنوان مدار محاسباتی پایه در طراحی سامانه‌های دیجیتال از اهمیت ویژه‌ای برخوردار است. در این مقاله، یک مدار نیم جمع¬کننده، یک مدار نیم تفریق¬کننده و سه مدار جمع‌کننده جدید در فناوری QCA و به کمک بلوک GDI بهبودیافته، طراحی شده است. شبیه‌سازی این مدارها با استفاده از نرم‌افزار QCADesigner و در فناوری 18 نانومتر مزیت‌های استفاده هم‌زمان از فناوری QCA و روش GDI به‌صورت هم‌زمان را نشان می¬دهد. نتایج حاصل از مقایسه و ارزیابی مدارهای پیشنهادی نسبت به بهترین جمع‌کننده موجود، بیانگر کاهش تا حدود 55% در مساحت اشغالی، کاهش محسوس تعداد سلول‌ها و تأخیری برابر و یا کمتر تا 28% نسبت به کارهای موجود است.
With the design of circuits at the nano-scale and observation of the problems of CMOS technology, designers are seeking suitable alternatives for this technology. Quantum-dot Cellular Automata (QCA) is one of these proposed technologies, which has attracted researchers' attention due to its high speed and low power consumption. On the other hand, the Gate Diffusion Input (GDI) method is an approach to improve power and area efficiency, which has led to higher speed, less power loss, and reduced complexity in Boolean functions through the use of fewer transistors. Furthermore, the adder, as a fundamental computational circuit in the design of digital systems, is of special importance. In this paper, a half-adder circuit, a half-subtractor circuit, and three new adder circuits in QCA technology have been designed and improved with the help of the GDI block. Simulation of these circuits using the QCADesigner software in 18-nanometer technology demonstrates the advantages of simultaneously using QCA technology and the GDI method. The results of the comparison and evaluation of the proposed circuits relative to the best existing adder indicate a reduction of about 55% in the occupied area, a significant decrease in the number of cells, and a delay that is equal to or less than 28% compared to existing works.
[1] M. Sadeghi, K. Navi, and M. Dolatshahi, “Novel efficient full adder and full subtractor designs in quantum cellular automata,” J. Supercomput., vol. 76, no. 3, pp. 2191–2205, 2020, doi: 10.1007/s11227-019-03073-4.
[2] S. D. R., T. K., J. B. B. Rayappan, R. Amirtharajan, and P. Praveenkumar, “MUX induced Ring oscillators for encrypted Nano communication via Quantum Dot Cellular Automata,” Nano Commun. Netw., vol. 27, p. 100338, 2021, doi: 10.1016/j.nancom.2020.100338.
[3] A. Ghorbani, M. Dolatshahi, S. M. Zanjani, and B. Barekatain, “A New Low Power, Area Efficient 4-bit Carry Look Ahead Adder in CNFET Technology,” Majlesi J. Electr. Eng., vol. 16, no. 1, pp. 65–73, 2022, doi: 10.52547/mjee.16.1.65.
[4] A. Ghorbani, M. Dolatshahi, S. M. Zanjani, and B. Barekatain, “A new low-power Dynamic-GDI full adder in CNFET technology,” Integration, vol. 83, no. December 2020, pp. 46–59, 2022, doi: 10.1016/j.vlsi.2021.12.001.
[5] L. Dehbozorgi, R. Sabbaghi-Nadooshan, and A. Kashaninia, “Novel Fault-Tolerant Processing in Memory Cell in Ternary Quantum-Dot Cellular Automata,” J. Electron. Test. Theory Appl., vol. 38, no. 4, pp. 419–444, 2022, doi: 10.1007/s10836-022-06018-7.
[6] S. S. Ahmadpour and M. Mosleh, “A novel fault-tolerant multiplexer in quantum-dot cellular automata technology,” J. Supercomput., vol. 74, no. 9, pp. 4696–4716, 2018, doi: 10.1007/s11227-018-2464-9.
[7] W. Liu, L. Lu, M. O’Neill, and E. E. Swartzlander, “Design rules for Quantum-dot Cellular Automata,” Proc. - IEEE Int. Symp. Circuits Syst., pp. 2361–2364, 2011, doi: 10.1109/ISCAS.2011.5938077.
[8] E. Abiri, M. R. Salehi, and A. Darabi, “Design and evaluation of low power and high speed logic circuit based on the modified gate diffusion input (m-GDI) technique in 32nm CNTFET technology,” 22nd Iran.Conf. Electr. Eng. ICEE 2014, no. Icee, pp. 67–72, 2014, doi: 10.1109/IranianCEE.2014.6999505.
[9] M. Shoba and R. Nakkeeran, “GDI based full adders for energy efficient arithmetic applications,” Eng. Sci. Technol. an Int. J., vol. 19, no. 1, pp. 485–496, 2016, doi: 10.1016/j.jestch.2015.09.006.
[10] S. R. M. CHANDRA and R. P. RAMANA, “Design and Implementation of Low Power Alu Using 8T Full Adder With Finfets,” i-manager’s J. Circuits Syst., vol. 5, no. 4, p. 8, 2017, doi: 10.26634/jcir.5.4.13939.
[11] A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, and A. Fish, “Full-swing gate diffusion input logic - Case-study of low-power CLA adder design,” Integr. VLSI J., 2014, doi: 10.1016/j.vlsi.2013.04.002.
[12] A. T. Mahani and P. Keshavarzian, “A novel energy-efficient and high speed full adder using CNTFET,” Microelectronics Journal, vol. 61. pp. 79–88, 2017. doi: 10.1016/j.mejo.2017.01.009.
[13] H. Arfavi, S. M. Riazi, and R. Hamzehyan, “Evaluation of Temperature, Disturbance and Noise Effect in Full Adders Based on GDI Method,” J. South. Commun. Eng., vol. 13, no. 50, pp. 47–66, 2023, doi: 10.30495/jce.2023.1973764.1197.
[14] H. Sadrarhami, S. M. Zanjani, M. Dolatshahi, B. Barekatain, and G. Scholar, “Innovation of a Novel Low-Power Modified-GDI QCA-Based Logic Circuit,” 2023, doi: 10.20944/preprints202311.1295.v1.
[15] P. D. Tougaw and C. S. Lent, “Logical devices implemented using quantum cellular automata,” J. Appl. Phys., vol. 75, no. 3, pp. 1818–1825, 1994, doi: 10.1063/1.356375.
[16] S. Perri, F. Spagnolo, F. Frustaci, and P. Corsonello, “Multibit Full Comparator Logic in Quantum-Dot Cellular Automata,” IEEE Trans. Circuits Syst. II Express Briefs, vol. 69, no. 11, pp. 4508–4512, 2022, doi: 10.1109/TCSII.2022.3193561.
[17] M. Sadeghi, K. Navi, and M. Dolatshahi, “A new quantum-dot cellular automata full-adder,” Proc. 2016 5th Int. Conf. Comput. Sci. Netw. Technol. ICCSNT 2016, vol. 41, no. 12, pp. 443–445, 2017, doi: 10.1109/ICCSNT.2016.8070197.
[18] I. Edrisi Arani and A. Rezai, “Novel circuit design of serial–parallel multiplier in quantum-dot cellular automata technology,” J. Comput. Electron., vol. 17, no. 4, pp. 1771–1779, 2018, doi: 10.1007/s10825-018-1220-y.
[19] S. R. Heikalabad, A. H. Navin, and M. Hosseinzadeh, “Content addressable memory cell in quantum-dot cellular automata,” Microelectron. Eng., vol. 163, pp. 140–150, 2016, doi: 10.1016/j.mee.2016.06.009.
[20] S. Angizi, S. Sarmadi, S. Sayedsalehi, and K. Navi, “Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata,” Microelectronics J., vol. 46, no. 1, pp. 43–51, 2015, doi: 10.1016/j.mejo.2014.10.003.
[21] H. Rashidi, A. Rezai, and S. Soltany, “High-performance multiplexer architecture for quantum-dot cellular automata,” J. Comput. Electron., vol. 15, no. 3, pp. 968–981, 2016, doi: 10.1007/s10825-016-0832-3.
[22] S. Bhanja, M. Ottavi, F. Lombardi, and S. Pontarelli, “Novel designs for thermally robust coplanar crossing in QCA,” in 2006 Design, Automation and Test in Europe, IEEE Computer Society, 2006, pp. 6-pp.
[23] S.-H. Shin, J.-C. Jeon, and K.-Y. Yoo, “Design of wire-crossing technique based on difference of cell state in quantum-dot cellular automata,” Int. J. Control Autom., vol. 7, no. 4, pp. 153–164, 2014.
[24] S. Hashemi, M. Rahimi Azghadi, and K. Navi, “Design and analysis of efficient QCA reversible adders,” J. Supercomput., vol. 75, no. 4, pp. 2106–2125, 2019, doi: 10.1007/s11227-018-2683-0.
[25] S. R. Fam and N. J. Navimipour, “Design of a loop-based random access memory based on the nanoscale quantum dot cellular automata,” Photonic Netw. Commun., vol. 37, no. 1, pp. 120–130, 2019, doi: 10.1007/s11107-018-0801-9.
[26] G. Singh, R. K. Sarin, and B. Raj, “A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis,” J. Comput. Electron., vol. 15, no. 2, pp. 455–465, 2016, doi: 10.1007/s10825-016-0804-7.
[27] Y. Zhang, F. Deng, X. Cheng, and G. Xie, “A Coplanar XOR Using NAND-NOR-Inverter and Five-Input Majority Voter in Quantum-Dot Cellular Automata Technology,” Int. J. Theor. Phys., vol. 59, no. 2, pp. 484–501, 2020, doi: 10.1007/s10773-019-04343-w.
[28] N. Safoev and J. C. Jeon, “A novel controllable inverter and adder/subtractor in quantum-dot cellular automata using cell interaction based XOR gate,” Microelectron. Eng., vol. 222, p. 111197, 2020, doi: 10.1016/j.mee.2019.111197.
[29] K. Navi, S. Sayedsalehi, R. Farazkish, and M. R. Azghadi, “Five-input majority gate, a new device for quantum-dot cellular automata,” J. Comput. Theor. Nanosci., vol. 7, no. 8, pp. 1546–1553, 2010, doi: 10.1166/jctn.2010.1517.
[30] S. Angizi, E. Alkaldy, N. Bagherzadeh, and K. Navi, “Novel robust single layer wire crossing approach for Exclusive OR Sum of Products logic design with Quantum-dot Cellular Automata,” J. Low Power Electron., vol. 10, no. 2, pp. 259–271, 2014, doi: 10.1166/jolpe.2014.1320.
[31] M. Poorhosseini and A. R. Hejazi, “A Fault-Tolerant and Efficient XOR Structure for Modular Design of Complex QCA Circuits,” J. Circuits, Syst. Comput., vol. 27, no. 7, 2018, doi: 10.1142/S0218126618501153.
[32] L. Wang and G. Xie, “A Novel XOR/XNOR Structure for Modular Design of QCA Circuits,” IEEE Trans. Circuits Syst. II Express Briefs, vol. 67, no. 12, pp. 3327–3331, 2020, doi: 10.1109/TCSII.2020.2989496.
[33] S. R. Kassa, R. K. Nagaria, and R. Karthik, “Energy efficient neoteric design of a 3-input Majority Gate with its implementation and physical proof in Quantum dot Cellular Automata,” Nano Commun. Netw., vol. 15, pp. 28–40, 2018, doi: 10.1016/j.nancom.2018.02.001.
[34] S. Sayedsalehi, M. H. Moaiyeri, and K. Navi, “Novel efficient adder circuits for quantum-dot cellular automata,” J. Comput. Theor. Nanosci., vol. 8, no. 9, pp. 1769–1775, 2011, doi: 10.1166/jctn.2011.1881.
[35] L. Wang and G. Xie, “Novel designs of full adder in quantum-dot cellular automata technology,” J. Supercomput., vol. 74, no. 9, pp. 4798–4816, 2018, doi: 10.1007/s11227-018-2481-8.
[36] M. Mosleh, “A Novel Full Adder/Subtractor in Quantum-Dot Cellular Automata,” Int. J. Theor. Phys., vol. 58, no. 1, pp. 221–246, 2019, doi: 10.1007/s10773-018-3925-x.
[37] Y. Adelnia and A. Rezai, “A Novel Adder Circuit Design in Quantum-Dot Cellular Automata Technology,” Int. J. Theor. Phys., vol. 58, no. 1, pp. 184–200, 2019, doi: 10.1007/s10773-018-3922-0.
[38] N. Safoev and J. C. Jeon, “Design of high-performance QCA incrementer/decrementer circuit based on adder/subtractor methodology,” Microprocess. Microsyst., vol. 72, p. 102927, 2020, doi: 10.1016/j.micpro.2019.102927.
[39] J. Maharaj and S. Muthurathinam, “Effective RCA design using quantum dot cellular automata,” Microprocess. Microsyst., vol. 73, p. 102964, 2020, doi: 10.1016/j.micpro.2019.102964.
[40] H. R. Roshany and A. Rezai, “Novel Efficient Circuit Design for Multilayer QCA RCA,” Int. J. Theor. Phys., vol. 58, no. 6, pp. 1745–1757, 2019, doi: 10.1007/s10773-019-04069-9.
[41] U. B. Joy, S. Chakraborty, S. Tasnim, M. S. Hossain, A. H. Siddique, and M. Hasan, “Design of an Area Efficient Quantum Dot Cellular Automata Based Full Adder Cell Having Low Latency,” Int. Conf. Robot. Electr. Signal Process. Tech., pp. 689–693, 2021, doi: 10.1109/ICREST51555.2021.9331135.
