Memristor, as a fundamental element of SRAM and DRAM memories, can effectively reduce startup time and power consumption of the circuits. Non-volatility, high density of the final circuit, and reduction of power delay product (PDP) are some of the significant facts of m More
Memristor, as a fundamental element of SRAM and DRAM memories, can effectively reduce startup time and power consumption of the circuits. Non-volatility, high density of the final circuit, and reduction of power delay product (PDP) are some of the significant facts of memristor circuits, which has led to the suggestion of a memory cell including and four transistors and two memristors (4T2M) in this paper. In order to simulate the proposed memory cell, the length of memristors has been selected 10 nm, and their on/off state resistors have been selected 250 Ω and 10 KΩ respectively. In addition, the proposed memory cell MOS transistors are simulated by the 32 nm CMOS PTM model. Simulation in the HSPICE software with 1V supply voltage and comparison with two conventional six-transistor (6T) and two transistors-two memory (2T2M) cells show that the use of memristors has made the proposed memory cell and 2T2M cell non-volatile. Moreover, the power consumption of the proposed circuit has decreased by 99.8% and 57.2%, compared to the previous two circuits respectively, and the power average delay product has also improved by 99.4% and 26.7%, respectively; however, the writing delay of this cell and 2T2M cell increased by 400% and 218% compared to 6T cell, respectively.
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Memristor is the fourth fundamental element after resistor, capacitor, and inductor. Memristor can become an essential element of SRAM and DRAM caches because of its zero power consumption in data storage and non-volatile state. It can effectively improve the efficiency More
Memristor is the fourth fundamental element after resistor, capacitor, and inductor. Memristor can become an essential element of SRAM and DRAM caches because of its zero power consumption in data storage and non-volatile state. It can effectively improve the efficiency, speed, and power consumption of circuits. In this paper, we propose a 4T1M memory cell reducing the cell area by maintaining the maximum properties of 6T1M. To simulate the proposed memory cell, the length of the memristors is 10 nm, and the resistance of their on and off states is selected as 1 kΩ and 200 kΩ, respectively. Also, the cell MOS transistors are simulated by the 32 nm HP CMOS PTM model. Simulations in H-Spice software, at 0.9 V power supply, have been conducted to compare the proposed cell characteristics with two conventional six-transistor (6T) and six-transistor one-memristor (6T1M) cells. The results show that using a memristor in a memory cell causes zero power consumption during data storage for a long time and reduces the occupied area by 36.7% compared to the 6T1M cell. The speed of writing “1” data on the proposed cell is only 30 ps, which shows a 3-fold improvement compared to the 6T1M cell, but no significant change is observed when writing “0” data. The static power of the proposed cell is 133 times less than that of a six-transistor cell, and its dynamic power is about the same as the 6T1M cell, but it consumes 60 times less energy than a six-transistor cell.
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Implementation of neuromorphic computing systems (NCSs) using digital and analog circuits occup­ies a high chip area and consumes high power. With the advancement of nanotechnology, the hybrid Magnetic tunnel junction/Complementary metal–oxide–semiconduc More
Implementation of neuromorphic computing systems (NCSs) using digital and analog circuits occup­ies a high chip area and consumes high power. With the advancement of nanotechnology, the hybrid Magnetic tunnel junction/Complementary metal–oxide–semiconductor (MTJ/CMOS) circuits have made it possible to implement NCSs with higher density and lower power consumption. However, still there is a gap between the performance of the human brain and NCSs. To mitigate this gap, it is essential to further decrease the energy consumption and the delay of the NCS. The high energy consumption of the MTJ-based NCS is mostly related to the high current needed to switch the MTJ state. Hence, some previous methods tried to perform real-time tracking of the MTJ state by monitoring its voltage and cutting off its current immediately after switching. However, due to the small voltage changes after switching, these methods suffer from a high-power consumption (they need power-hungry amplifiers). In this paper, a new method based on the tracking of MTJ current (instead of voltage) and terminating the MTJ current after switching is proposed. Due to the large changes in the MTJ current after switching (about 40%), there is no need to use an amplifier in the proposed circuit. Therefore, the conventional voltage-mode sensing circuit is replaced with the proposed circuit, to improve the energy efficiency, speed and delay of the NCS. In all state-of-the-art designs, the voltage changes on nodes across the MTJ (PL, FL or both of them) have been used to detect the MTJ switching. However, the proposed circuit detects the MTJ switching by properly sensing the MTJ current and terminates its current immediately. The simulation results in 65-nm CMOS technology confirm that the proposed technique improves the energy consumption and speed of the NCS by 49% and 2.1X compared with the typical NCS.
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