Design and Simulation of Low Power Adder Circuits Using MGDI Gate in QCA Technology

Subject Areas : Electrical and Computer Engineering

Hamidreza  Sadrarhami ¹ (Faculty of Computer Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran)
Sayed Mohammadali   Zanjani ² (Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran)
Mehdi  Dolatshahi ³ (Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran)
Behrang  Barekatain ⁴ (Faculty of Computer Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran)

Received: 2024-01-23 Accepted : 2024-03-31 Published : 2024-07-03

Keywords: Quantum-dot cellular automata, Gate diffusion input, Low power, Nanotechnology, Full adder,

Abstract :

With the design of circuits at the nano-scale and observation of the problems of CMOS technology, designers are seeking suitable alternatives for this technology. Quantum-dot Cellular Automata (QCA) is one of these proposed technologies, which has attracted researchers' attention due to its high speed and low power consumption. On the other hand, the Gate Diffusion Input (GDI) method is an approach to improve power and area efficiency, which has led to higher speed, less power loss, and reduced complexity in Boolean functions through the use of fewer transistors. Furthermore, the adder, as a fundamental computational circuit in the design of digital systems, is of special importance. In this paper, a half-adder circuit, a half-subtractor circuit, and three new adder circuits in QCA technology have been designed and improved with the help of the GDI block. Simulation of these circuits using the QCADesigner software in 18-nanometer technology demonstrates the advantages of simultaneously using QCA technology and the GDI method. The results of the comparison and evaluation of the proposed circuits relative to the best existing adder indicate a reduction of about 55% in the occupied area, a significant decrease in the number of cells, and a delay that is equal to or less than 28% compared to existing works.

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