Analysis of the effect of changes of FINs Architectural on FINFET Drain current and on Average Power Dissipation and Propagation Delay in the Hybrid-CMOS full adder
Subject Areas : Electronics Engineering
Teimoor Rashedzadeh
1
,
Seyed Mohammad Ali Riyazi
2
,
Najmeh Cheraghi Shirazi
3
1 - Electrical Engineering, Islamic Azad University, Bushehr Branch, Bushehr, Iran
2 - Electrical Engineering, Islamic Azad University, Bushehr Branch, Bushehr, Iran
3 - department of electrical engineering, bushehr branch, islamic azad university, bushehr, iran
Keywords:
Abstract :
In this paper, full adder circuit with Hybrid-CMOS logic style is proposed which is a combination of pass transistors and transmission gates and N & P type transistors. For design full adder circuitry using FINFET transistors, BSIM-CMG model, Dual-gate and bulk FINFET structure using 16nm Gate length and HSPICE simulation. due to the structure and architecture of the FINFET transistors, the effect of changes in thickness and height and the number of FINs on the Drain current of the FINFET transistor and output parameters such as average power dissipation and propagation delay of the full adder cell and also the effect of changes in inputs frequency of full adder are investigated. According to the simulation results, with increasing thickness and height and the number of FINs, average power dissipation increases and propagation delay decreases, and vice versa. As well as increasing the operating frequency up, average power dissipation increases.
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[8] A. B. A. Tahrimet. al,“Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16nm Process Technology,”Hindawi Publishing Corporation Journal of Nanomaterials, vol.2015, 2015.
[9] P. Jay and A. D. Darji, "Analysis of the source/drain parasitic resistance and capacitance depending on geometry of FinFET," 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2015, pp. 298-301.
[10] T. Hayashida et. al, “Fin-Height Effect on Poly-Si/PVD-TiNStacked-Gate FINFET Performance,” IEEE Transactions on Electron Devices,vol. 59, no.3, pp. 647 - 653 , March 2012.
[11] M. K. Rai, V. Narendar and R. A. Mishra, "Significance of variation in various parameters on electrical characteristics of FinFET devices," 2014 Students Conference on Engineering and Systems, 2014, pp. 1-6, [12] J.-P. Colinge, “Silicon-on-Insulator Technology: Materials to VLSI”, Springer, NewYork USA, 2004. [13] R. Kumar et. al,” Low-Power High-Speed Double Gate 1-bit Full Adder Cell ,” Intel Journal of Electrpnics and Telecommunications ,vol. 62, no. 4, pp. 329-334, 2016.
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[1] I. Ferain, C. A. Colinge, and J-P Colinge, "Multi-gate Transistors as the future of classical Metal-oxide-semiconductor Field-effect Transistors." Nature, vol.479, pp.310-316, Nov. 2011.
[2] M. Zhang, J. Gu, and C. H. Chang, “A Novel Hybrid Pass Logic With Static CMOS Output Drive Full-adder Cell,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2003, pp. 317–320 .
[3] J.-P. Colinge, “FinFETs and Other Multi-Gate Transistors,” Springer,USA, 2008
[4] J-H. Lee, “Bulk FinFETs: Design at 14 nm Node and Key Characteristics” Springer Science, vol.65, pp.33-64, 2016.
[5] J. Whitehouse and E. John, "Leakage and delay analysis in FinFET array multiplier circuits," IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014, pp. 909-912
[6] Y. S. Chauhan et. al, “BSIM Compact MOSFET Models for SPICE Simulation,” Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES, June 2013, pp.23-28.
[7] S. Goel, A. Kumar and M. A. Bayoumi, "Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 12, pp. 1309-1321, Dec. 2006.
[8] A. B. A. Tahrimet. al,“Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16nm Process Technology,”Hindawi Publishing Corporation Journal of Nanomaterials, vol.2015, 2015.
[9] P. Jay and A. D. Darji, "Analysis of the source/drain parasitic resistance and capacitance depending on geometry of FinFET," 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2015, pp. 298-301.
[10] T. Hayashida et. al, “Fin-Height Effect on Poly-Si/PVD-TiNStacked-Gate FINFET Performance,” IEEE Transactions on Electron Devices,vol. 59, no.3, pp. 647 - 653 , March 2012.
[11] M. K. Rai, V. Narendar and R. A. Mishra, "Significance of variation in various parameters on electrical characteristics of FinFET devices," 2014 Students Conference on Engineering and Systems, 2014, pp. 1-6, [12] J.-P. Colinge, “Silicon-on-Insulator Technology: Materials to VLSI”, Springer, NewYork USA, 2004. [13] R. Kumar et. al,” Low-Power High-Speed Double Gate 1-bit Full Adder Cell ,” Intel Journal of Electrpnics and Telecommunications ,vol. 62, no. 4, pp. 329-334, 2016.