Design of high linearity large dynamic-range delay-element for low-voltage low-power applications

Subject Areas : Electronics Engineering

آتنا Varzandeh Esfahani ¹ (گروه برق، پردیس علوم و تحقیقات خراسان رضوی، دانشگاه آزاد اسلامی)
S. M Fahmideh Akbarian ² (گروه برق، موسسه آموزش عالی خراسان)

Received: 2015-01-07 Accepted : 2016-04-12 Published : 2015-07-14

Keywords:

Abstract :

Designing a high efficiency delay-element is a challenge for low-power low-voltage digital circuits. The delay element circuit has a considering effect on efficiency of low-voltage digital circuits. In sub-micron technologies that lowering the power and the voltage of the systems is essentially required, design of a highly linear large dynamic range delay element is an important issue for designers. In this paper high linearity delay element is proposed employing the sub-threshold source coupled logic (STSCL) circuits. The presented circuit has a considerable controlling of the delay value by a control voltage. Improvements of dynamic-range and the linearity of the circuit show the operation of the delay element in sub-threshold region.

References:

1. Tajalli, E. J. Brauer, Y. Leblebici and E. Vittoz (2008), Sub-threshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications, in IEEE JOURNALS of Solid-State Circuits, VOLUME: 43, Issue: 7, page(s): 1699-1710.


2. Tajalli and Y. Leblibici (2009), Sub-threshold leakage reduction: A comparative study of SCL and CMOS design, in IEEE International Symposium of Circuits and Systems, ISCAS 2009


3. قاسمی، عبدالرسول و احسان رحیمی نژاد، ۱۳۹۴، "استفاده از منطق STSCL برای تولید المان تأخیر با توان مصرفی کم برای کاربرد در مبدل آنالوگ به دیجیتال تمام دیجیتال"، کنفرانس ملی فن آوری، انرژی و داده با رویکرد مهندسی برق و کامپیوتر، کرمانشاه
   
   
   1. Tajalli, Y. Leblebici, and E.J. Brauer, ”Implementing ultra high value tunable CMOS resistors,” IEE Electronics Letters, vol. 44, no. 5, pp. 349-350, Feb. 2008.
   
   
   2. Tajalli, P. Muller, M. Atarodi, and Y. Leblebici,“A multichannel 3.5mW/Gb/s/channel gated oscillator based CDR in a 0.18m dig-ital CMOS technology,”inProc. Eur. Solid-State Circuits Conf. (ESS-CIRC), Grenoble, France, Sep. 2005, pp. 193–196
   
   
   3. M. Azaga and M. Othman (2008), Source Couple Logic (SCL): Theory and Physical Design, in American Journal of Engineering and Applied Sciences 1 (1), page(s): 24-32.
   
   
   4. Enz, F. Krummenacher, E. Vittoz, Charged based MOS transistor Modeling: The EKV Model for Low-Power and RF-IC Design. New York: Wiley, 2006.
   
   
   5. Enz, F. Krummenacher, E. Vittoz (1995), An analytical MOS transistor Model valid in all regions of operation and dedicated to low-voltage and low-current applications, Analog Integrated. Circuits Signal Process. J. volume 8, page(s) 83-114.
   
   
   6. Vittoz, Weak Inversion for Ultra Low-Power and Very Low-Voltage Circuits (2009), in IEEE Asian Solid-State Circuits Conference, pages(s): 129-132.
   
   
   7. T. Darwish and M. Bayoumi (2005), Trends in Low-Power VLSI Design, in the center for Advanced Computer Studies, University of Loisiana at Lafayette, Lafayette, Louisiana, USA.
   
   
   8. Mohammad Beikahmadi, Armin Tajalli, and Yusuf Leblebici, A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC, Microelectronic Systems Lab. (LSM), Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland, 1-4244-2493-1/08/, 2008 IEEE.
   
   
   9. Tajalli, P. Muller, and Y. Leblebici, “A power-efficient clock and data recovery circuit in 0.18-m CMOS technology for multi-channel short-haul optical data communication,”IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2235–2244, Oct. 2007