Design of high linearity large dynamic-range delay-element for low-voltage low-power applications

Subject Areas : Electronics Engineering

آتنا Varzandeh Esfahani ¹ , S. M Fahmideh Akbarian ²

1 - گروه برق، پردیس علوم و تحقیقات خراسان رضوی، دانشگاه آزاد اسلامی
2 - گروه برق، موسسه آموزش عالی خراسان

Received: 2015-01-07 Accepted : 2016-04-12 Published : 2015-07-14

Keywords:

Abstract :

Designing a high efficiency delay-element is a challenge for low-power low-voltage digital circuits. The delay element circuit has a considering effect on efficiency of low-voltage digital circuits. In sub-micron technologies that lowering the power and the voltage of the systems is essentially required, design of a highly linear large dynamic range delay element is an important issue for designers. In this paper high linearity delay element is proposed employing the sub-threshold source coupled logic (STSCL) circuits. The presented circuit has a considerable controlling of the delay value by a control voltage. Improvements of dynamic-range and the linearity of the circuit show the operation of the delay element in sub-threshold region.

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