Design and simulation of fully integrated low-power amplifier (LNA) with 0.18 Cm CMOS technology in 1.9 and 0.9 GHz frequencies

Subject Areas : Electronics Engineering

Ebrahim  Abiri Jahromi ¹ (Shiraz University of Technology)
raziyeh  Soltani Sarvestani ² (Islamic Azad University, Bushehr Branch, Bushehr , Iran)

Received: 2021-04-27 Accepted : 2021-04-27 Published : 2019-01-21

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Abstract :

Two important parameters that should be considered in the design of a low noise amplifier (LNA) are low power consumption and low noise number. Other design problems include how to create a stable 50 ohm resistor at the input to adjust impedance while increasing gain. Also, how to linearize over a wide range of operating frequencies is an important issue to consider. Using the structure of selfie degeneration in the 0.18 µm CMOS process, the desired requirements are met. The circuit proposed in this paper has a noise number of less than 2.5db and power consumption of less than 4mw at a frequency of 1.9 and a noise number of less than 0.7db and power consumption of less than 0.9mw at a frequency of 0.9 GHz, matching the input impedance and Outputs 50 Ohms and results in proper linearization at both frequencies.