Low-offset and high-gain up-amp design in analog to digital cyclic converter Twelve bits for CMOS image sensor

Subject Areas : Electronics Engineering

1 - Islamic Azad University, Faculty member
2 - Islamic Azad University, Bushehr Branch, Department of Electronics, Bushehr, Iran

Received: 2021-05-22 Accepted : 2021-05-22 Published : 2017-04-21

Keywords:

Abstract :

In this paper, an analog-to-digital twelve-bit cyclic converter with high speed and accuracy and yet low power is proposed. Requires a wide dynamic range and high speed and high accuracy, which is suggested in this article. Finally, this circuit was simulated with HSPICE software and acceptable results were obtained. This circuit requires a voltage of 3.3 and in The technology is 0.35. The power consumption is 11 mW and the SFDR is 66 dB and the THD is 2 - and the SNDR is 40 dB. Shooting for different setting conditions.

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Low-offset and high-gain up-amp design in analog to digital cyclic converter Twelve bits for CMOS image sensor