Presentation of hardware method of error reduction in electronic devices of quantum nanosatellites
Subject Areas : Electronics Engineering
Mojdeh Mahdavi
1
(Islamic Azad University, Shahr-e-Quds Branch, Department of Electronic Engineering, Tehran, Iran)
Mohammad Amin Amiri
2
(Islamic Azad University, Shahr-e-Quds Branch, Department of Electronic Engineering, Tehran, Iran)
Vahid sadatpour
3
(Islamic Azad University, Science and Research Branch, Department of Computer Engineering, Tehran, Iran)
Keywords:
Abstract :
Today, space technology is recognized as one of the competitive fields among countries and the various achievements of space technology are an accurate basis for comparing countries in terms of industrial development. In the near future, nanosatellites will become the main trend in the development of regional terrestrial monitoring and positioning. The turnover of a satellite is millions of dollars, so a significant part of each country's investment is in the aerospace sector, and in the event of failure, a large cost will be imposed on the manufacturer. For this reason, before launching a satellite, considerations are made so that the satellites can perform the assigned operations without the slightest error. Until now, the use of microelectronic circuits has been common in space applications due to their advantages, including availability and reconfigurability, but these components are vulnerable to the radiation environment. On the other hand, due to the rapid changes in electronics to nanotechnology and the advantages of nanoelectronic circuits, in the not too distant future, nanoelectronics components will be a viable alternative in space applications. As the size of the components decreases, the orbits become more sensitive and the quantum circuits become more vulnerable to radiation from space. In this paper, we present the method of increasing the fault tolerance and their simulation in the binary wire of nanosatellites in quantum cellular automation technology.
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