This paper, describes a CMOS trans-impedance amplifier (TIA) and Limiting Amplifier (LA) for 2.5Gb/s, low-power opto-electronic communication receiver systems. The single ended TIA, which benefits form active type of inductors, is designed and simulated using 0.18µm CMOS process parameters. The proposed circuits are analyzed mathematically and all necessary simulations for proving the proper performance of the proposed TIA stage and the proposed LA stage such as eye-diagram, MONTECARLO and noise analysis are done. Simulation results in HSPICE show the trans-impedance gain of 45.5dBΩ, frequency bandwidth of 1.85GHz and power consumption of 1.1mW at 1.5V supply for the TIA stage and 87dB gain and 2GHz frequency bandwidth for the whole receiver system, which consumes only 7.3mW power. Results indicate that the proposed circuits are suitable to work as a low-power building block as opto-electrical communication receiver. Manuscript profile

In this paper, a one-bit ultra-low-power full adder cell using GDI structure is proposed. Main objective of this design is not only providing low power consumption, but also providing full swing outputs. In this paper, combination of different logics and stacking technique are used to provide an ultra-low power cell. Also, by using stacked inverters after each function, full swing characteristic for the cell is obtained. These characteristics are obtained in cost of more occupied chip area and higher delay. In order to verify the performance of the proposed cell, simulations are done in HSPICE using 90nm CMOS technology library. Beside Noise immunity, power consumption is also analyzed under different load conditions, different supply voltages and different temperatures. Although delay of the circuit is increased, results show a tremendous reduction in power consumption and an improved power-delay-product for the proposed full adder cell. Manuscript profile