Dependability of a circuit is among the most important issues in the design process and reliability concerns are associated with the digital system design. A fault tolerant system should have the ability to detect, locate and correct the error and recover the system to normal operational conditions. It is more important to use fault tolerant gates in nano scale digital circuits because by decreasing the device dimensions the influence of external factors and therefore the probability of fault occurrence will increase. Since the binary wire is an essential part of digital systems and especially QCA (Quantum Cellular Automata) circuits, a redundancy based fault tolerant technique is presented in this paper to improve the fault tolerance of this part. The efficiency of this method is evaluated by MATLAB software. Results show that the fault tolerance of binary wire will significantly increase by using the proposed method. The hardware redundancy of this method is about 100% which is much less than TMR (Triple Module Redundancy) methods by more than 200% redundancy. Manuscript profile

Lent has created QCA nanoscale devices by merging the cellular automata and quantum electronics. These devices are capable of achieving very high switching speeds and very low electrical power consumption. AES block cipher is now used worldwide. This algorithm is based on the Rijndael cipher which was submitted as a proposal to NIST during the AES selection process. The implementation of this cryptographic algorithm in QCA technology is presented in this paper. On the other hand, the QCADesigner software which is used to simulate QCA circuits is sensitive to the QCA cell count, inputs and outputs. It seems that by increasing the QCA cell count, inputs and outputs, the simulation time will increase and sometimes the simulation will be impossible. A higher level modeling of QCA circuits by VHDL hardware description language and simulation of these models by ModelSim software is presented in this paper to solve the mentioned problem. It is shown that the QCA implementation of the AES algorithm with key, input and output length of 128 bits is easily modeled and simulated in ModelSim software. The implementation results of various implementation methods are also compared in this paper for AES algorithm. It is illustrated that the QCA implementation of this algorithm is the most efficient implementation among existing methods. Manuscript profile

The heartbeat is triggered by a sinoatrial node in the heart. If the sinoatrial node is disrupted for any reason or if there is a problem with the heart's electrical signal path, the heart rate will decrease or become impaired; in which case the cardiac pacemaker could control the heart function. The pacemaker is an electrical stimulator that causes the heart to expand and contract and triggers pulses to the heart when needed or permanently. Since the pacemaker is placed inside the patient's body, it should be designed based on the minimum power consumption. Besides, frequency adjustment in this device is necessary to regulate heart rate in a variety of arrhythmias. In this paper, logic cells of quantum cellular automata are utilized to design a pulse generator circuit in a heart oscillator, where power consumption and dimensions are minimal. An important feature of the proposed circuit is the ability to adjust the output pulse frequency. The efficiency of this circuit has been evaluated using QCAdesigner simulator and desirable results have been obtained in terms of power consumption level. The simulation results also show very low power consumption for the designed circuit. Manuscript profile