Design and Simulation of a Low-Power Static Random-Access Memory (SRAM) Cell based on FinFET Transistor

Subject Areas : Electronic Engineering

Fatemeh  Zolfaghari Sichani ¹ (Department of Electrical Engineering, Isfahan (Khorasgan) Branch, Islamic Azad University, Isfahan, Iran)
Mohammad Rouhollah  Yazdani ² (Department of Electrical Engineering, Isfahan (Khorasgan) Branch, Islamic Azad University, Isfahan, Iran)
Atefeh  Salimi ³ (Department of Electrical Engineering, Isfahan (Khorasgan) Branch, Islamic Azad University, Isfahan, Iran)
Maryam  Monemian ⁴ (Medical image and signal processing research center, Isfahan University of medical sciences, Isfahan, Iran)

Received: 2023-02-14 Accepted : 2023-06-08 Published : 2025-03-19

Keywords: Static memory cell, Random-access, FinFET transistor, Power consumption,

Abstract :

Fin field-effect transistors (FinFETs) are good alternatives to conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) because of their potential for controlling the effects of short channel, leakage current, propagation delay and power loss. Since SRAMs occupy most of the advanced processors’ space, main power consumption in these processors is attributed to these memories. In a common 6-transistor static random access memory (6T SRAM) cell, the capacitors of both bit lines must be charged and discharged when reading and writing tasks are performed. Thus, most of the power consumption is related to this mechanism. In this paper, 7-Transistor static random-access memory (7T SRAM) cell is proposed that is able to write using one of the bit lines. The results of simulation using HSPICE software and in 32 nm technology show that the power consumption of this cell during write operation when the value "0" is stored in the cell is at most 98.6% and it has decreased by 99.8% when the value "1" is present in the cell. Also, the amount of Static Noise Margin (SNM) in standby and cell reading modes is equal to 0.2025 and 0.2011 volts respectively.

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