Design and Simulation of a Low-Power Static Random-Access Memory (SRAM) Cell Based on FinFET Transistor

Subject Areas : Electronic Engineering

Fatemeh Zolfaghari Sichani ¹ , Mohammad Rouhollah Yazdani ² , Atefeh Salimi ³ , Maryam Monemian ⁴

1 - Department of Electrical Engineering, Isfahan (Khorasgan) Branch, Islamic Azad University, Isfahan, Iran
2 - Department of Electrical Engineering, Isfahan (Khorasgan) Branch, Islamic Azad University, Isfahan, Iran
3 - Department of Electrical Engineering, Isfahan (Khorasgan) Branch, Islamic Azad University, Isfahan, Iran
4 - Medical image and signal processing research center, Isfahan University of medical sciences, Isfahan, Iran

Received: 2023-02-14 Accepted : 2023-06-08 Published : 2025-03-19

Keywords: Static memory cell, Random-access, FinFET transistor, Power consumption,

Abstract :

Fin field-effect transistors (FinFETs) are good alternatives to conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) because of their potential for controlling the effects of short channel, leakage current, propagation delay and power loss. Since SRAMs occupy most of the advanced processors’ space, main power consumption in these processors is attributed to these memories. In a common 6-transistor static random access memory (6T SRAM) cell, the capacitors of both bit lines must be charged and discharged when reading and writing tasks are performed. Thus, most of the power consumption is related to this mechanism. In this paper, 7-Transistor static random-access memory (7T SRAM) cell is proposed that is able to write using one of the bit lines. The results of simulation using HSPICE software and in 32 nm technology show that the power consumption of this cell during write operation when the value "0" is stored in the cell is at most 98.6% and it has decreased by 99.8% when the value "1" is present in the cell. Also, the amount of Static Noise Margin (SNM) in standby and cell reading modes is equal to 0.2025 and 0.2011 volts respectively.

References:

1. Y.H. Chen, W.M. Chan, W.C. Wu, H.J. Liao, K.H. Pan and J.J. Liaw, “A 16 nm 128 Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” IEEE J. Solid-State Circuits, vol. 50, no. 1, pp. 170–177. Jan. 2018, doi: 10.1109/JSSC.2014.2349977.


2. T. Kumar and S.L. Tripathi, “Implementation of CMOS SRAM Cells in 7, 8, 10 and 12-Transistor Topologies and their Performance Comparison,” International Journal of Engineering and Advanced Technology (IJEAT), vol. 8, pp. 227–229. Jan. 2019, doi: B10480182S219/19©BEIESP.


3. A. Bhaskar, “Design and analysis of low power SRAM cells,” in 2017 Innovations in Power and Advanced Computing Technologies (i-PACT), 2017, doi: 10.1109/IPACT.2017.8244888.


4. J. Shalf, “The future of computing beyond Moore’s Law,” Royal Society, Jan. 2020, doi: 10.1098/rsta.2019.0061.


5. T. Suzuki, H. Yamauchi, Y. Yamagami, K. Satomi and H. Akamatsu, “A stable 2-port SRAM cell design against simultaneously read/write-disturbed accesses,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 2109–2119, Sep. 2008, doi: 10.1109/JSSC.2008.2001872.


6. R.E. Aly and M.A. Bayoumi, “Low-Power Cache Design Using 7T SRAM Cell,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 4, pp. 318-322, Apr. 2007, doi: 10.1109/TCSII.2006.877276.


7. A. Teman, L. Pergament, O. Cohen and A. Fish, “A 250 mV 8 kb 40 nm ultra-low power 9T supply feedback SRAM (SF-SRAM),” IEEE Journal of Solid-State Circuits, vol. 46, pp. 2713–2726, Nov. 2011, doi: 10.1109/JSSC.2011.2164009.


8. M. Ansari, H. Afzali-Kusha, B. Ebrahimi, Z. Navabi, A. Afzali-Kusha and M. Pedram, “A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies,” INTEGRATION, the VLSI journal, vol. 50, pp. 91–106, Jun. 2015, doi: 10.1016/j.vlsi.2015.02.002.


9. A. Teman, A. Mordakhay, J. Mezhibovsky and A. Fish, “A 40-nm Sub-Threshold 5T SRAM Bit Cell with Improved Read and Write Stability,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, pp. 873–877, Dec. 2012, doi: 10.1109/TCSII.2012.2231020.


10. E. Seevinck, F. J. List and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE Journal of Solid-State Circuits, vol. 22, no. 5, pp. 748-754, Oct. 1987, doi: 10.1109/JSSC.1987.1052809.


11. Y.B. Kim, Y.B. Kim and F. Lombardi, “Low Power 8T SRAM Using 32nm Independent Gate FinFET Technology,” in 2008 IEEE International SOC Conference, Sep. 2008, doi: 10.1109/SOCC.2008.4641521.


12. R. Balwinder, A.K. Saxena and S. Dasgupta, “FinFET-based 6T SRAM cell design: analysis of performance metric, process variation and temperature effect,” Journal of Computational and Theoretical Nanoscience, vol. 12, pp. 2500–2506, Sep. 2015, doi: 10.1166/jctn.2015.4055.


13. V. Sikarwar, S. Khandelwal and S. Akashe, “Analysis and Design of Low Power SRAM Cell Using Independent Gate FinFET,” Radioelectron.Commun. Syst, 2013, vol. 56, pp. 434–440. doi: 10.3103/S0735272713090021.


14. M.S. Shairfe, M. Salahuddin and C. Mansun, “Eight- FinFET Fully Differential SRAM Cell with Enhanced Read and Write Voltage Margins,” IEEE Transactions on Electron Devices, vol. 62, pp. 2014–2021, May 2015, doi: 10.1109/TED.2015.2424376.


15. S. Sanjana, S. Ramakrishna, R. RBanu and P. Shubham, “Design and Performance Analysis of 6T Sram Cell in 22nm CMOS and FinFET Technology Nodes,” in 2017 International Conference on Recent Advances in Electronics and Communication Technology (ICRAECT), Mar. 2017. doi: 10.1109/ICRAECT.2017.65.


16. T.H. Kim, J. Liu, J. Keane and C.H. Kim, “Circuit techniques for ultra-low power subthreshold SRAMs,” IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, WA, USA, 2008, pp. 2574-2577, doi: 10.1109/ISCAS.2008.4541982.


17. J. Singh, D.K. Pradhan, S. Hollis, S.P. Mohanty and J. Mathew, “Single ended 6T SRAM with isolated read-port for low-power embedded systems,” Design, Automation & Test in Europe Conference & Exhibition, Nice, France, 2009, pp. 917-922, doi: 10.1109/DATE.2009.5090796.


18. T. Azam, B. Cheng and D.R. S. Cumming, “Variability resilient low-power 7T-SRAM design for nano-scaled technologies,” in 11th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, USA, 2010, pp. 9-14, doi: 10.1109/ISQED.2010.5450414.


19. A. Sil, S. Bakkamanthala, S. karlapudi and M. Bayoumi, “Highly stable, dual-port, sub-threshold 7T SRAM cell for ultra-low power application,” in 10th IEEE International NEWCAS Conference, Montreal, QC, Canada, 2012, pp. 493-496, doi: 10.1109/NEWCAS.2012.6329064.


20. D. Sylvester and T.N. Mudge, “Yield-driven near-threshold SRAM design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Dec. 2010. doi: 10.1109/TVLSI.2009.2025766.


21. P.F. Chiu, C.W. Wu, C.H. Chuang, S.S. Sheu, Y.S. Chen and M.J. Tsai, “Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM with Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications” IEEE Journal of Solid-State Circuits, vol. 47, no. 6, pp. 1483-1496, Jun. 2012, doi: 10.1109/JSSC.2012.2192661.


22. Z. Liu and V. Kursun, “Characterization of a Novel Nine-Transistor SRAM Cell,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 4, pp. 488-492, Apr. 2008, doi: 10.1109/TVLSI.2007.915499.


23. A.R. Ramani and K. Choi, “A novel 9T SRAM design in sub-threshold region,” IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY, Mankato, MN, USA, 2011, pp. 1-6, doi: 10.1109/EIT.2011.5978615.


24. M.H. Tu, J.Y. Lin, M.C. Tsai, C.Y. Lu,Y. J. Lin, M.H.Wang, H.S.Huang, K.D. Lee,W.C. Shih, S.J. Jou and C.T. Chuang, “A Single-Ended Disturb-Free 9T Subthreshold SRAM with Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing,” IEEE Journal of Solid-State Circuits, vol. 47, no. 6, pp. 1469-1482, Jun. 2012, doi: 10.1109/JSSC.2012.2187474.


25. S. Singh, N. Arora, N. Gupta and M. Suthar, “Leakage reduction in differential 10T SRAM cell using Gated VDD control technique,” International Conference on Computing, Electronics and Electrical Technologies (ICCEET), Nagercoil, India, 2012, pp. 610-614, doi: 10.1109/ICCEET.2012.6203867.


26. C.H. Lo and S.Y. Huang, “P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation,” IEEE Journal of Solid-State Circuits, vol. 46, no. 3, pp. 695-704, Mar. 2011, doi: 10.1109/JSSC.2010.2102571.


27. A.K. Singh, C.M.R. Prabhu, S. W. Pin and T. C. Hou, “A proposed symmetric and balanced 11-T SRAM cell for lower power consumption,” IEEE Region 10 Conference, Singapore, 2009, pp. 1-4, doi: 10.1109/TENCON.2009.5396237.


28. P. Upadhyay, R. Kar, D. Mandal and S.P. Ghoshal, “A design of low swing and multi threshold voltage based low power 12T SRAM cell,” Comput Electr Eng, Elsevier Ltd. Oct. 2014, doi: 10.1016/j.compeleceng.2014.10.020.


29. S.K. Srivastavar1 and E.A. Kumar, “Characterization of 6T CMOS SRAM in 65nm and 120nm Technology using Low Power Techniques,” International Research Journal of Engineering and Technology (IRJET), Volume: 04 Issue: 07, Jul. 2017.


30. T.H. Kim, J. Liu, J. Keane and C.H. Kim, “Circuit techniques for ultra-low power subthreshold SRAMs,” IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, WA, USA, 2008, pp. 2574-2577, doi: 10.1109/ISCAS.2008.4541982.


31. T.H. Kim, J. Liu, J. Keane and C.H. Kim, “A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-lowvoltage computing,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 518–529, Feb. 2008. doi: 10.1109/JSSC.2007.914328.


32. J. Chen, L.T. Clark and T.H. Chen, “An ultra-low-power memory with a subthreshold power supply voltage,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 2344–2353, Oct. 2006. doi: 10.1109/JSSC.2006.881549.


33. B.H. Calhoun and A. Chandrakasan, “A 256kb Sub-threshold SRAM in 65nm CMOS,” IEEE International Solid State Circuits Conference - Digest of Technical Papers, Feb. 2006. doi: 10.1109/ISSCC.2006.1696325.


34. H. Kumar and V.K. Tomar, “A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano‑Scale Era,” Wireless Personal Communications, vol. 117, pp. 1959–1984, Nov. 2020. doi: 10.1007/s11277-020-07953-4.


35. G. Torrens and B. Alorda, “A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors,” IEEE Transactions on Emerging Topics in Computing, vol. 7, pp. 445–457, Jul. 2019. doi: 10.1109/TETC.2017.2721932.


36. A. Gadhe and U. Shirode, “Read stability and Write ability analysis of different SRAM cell structures,” International Journal of Engineering Research and Applications (IJERA), Vol. 3, Issue 1, Jan. –Feb. 2013, pp.1073-1078. doi:10.1109/JSSC.2006.883344.


37. N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara and C. Anghel, “3T-TFET bitcell based TFET-CMOS Hybrid SRAM design for Ultra-Low Power Applications,” Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2016. doi:10.3850/9783981537079_0462.


38. Y.N. Chen, M.L. Fan, V.P.H. Hu, P. Su and C.-T. Chuang, “Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell with Write-assist Circuits,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 4, pp. 389-399, Dec. 2014. doi: 10.1109/JETCAS.2014.2361072.


39. S. Kumar V and A. Noor, “Characterization and comparison of low power sram cells,” Journal of Electron Devices, Vol. 11, 2011, pp. 560-566.