Simulation and Optimization of Dual Gate - Dual Material Tunnel Transistor

Subject Areas : Electronic Engineering

Reza  Talebzadeh ¹ (Engineering Department, Lorestan University, Lorestan, Iran)
Javad  Hasanvand ² (Engineering Department, Lorestan University, Lorestan, Iran)
Ali  Mir ³ (Engineering Department, Lorestan University, Lorestan, Iran)

Received: 2022-07-06 Accepted : 2022-10-05 Published : 2023-02-20

Keywords: Performance Improvement, Tunnel Transistor, Silvaco-Atlas, Simulation,

Abstract :

In this paper, we designed and simulated a new TFET. Due to the band-to-band tunneling current mechanism, the TFETs show a low current and subthreshold slope of less than 60mV/dec. As a result, they can be a suitable alternative to MOSFET for use in low-power switching circuits. But its main disadvantage is its low on-state current compared to MOSFET. In this article, an optimized two-gate-two-material tunnel transistor structure is proposed in which the tunneling rate of carriers increased by adding two regions with inherent impurity compared to the common two-gate TFET structures. We simulated the proposed TFET in two dimensions using Silvaco-Atlas software and analyzed its results. The results are as follows: the on-state current (Ion=5.49×10-6A/µm), off current (Ioff=2×10-18A/µm), Subthreshold slope (SS=15.02mV/dec), and the Ion/Ioff =2.74×1012. The calculated results show the improvement of the DC parameters of the device.

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