Introducing a new CMOS-MTJ architecture for fast and highly low power 4:2 approximate compressors: insights into their applications in image processing
Subject Areas : Electronic Engineering
1 - Islamic Azad University of yazd
Keywords: Approximate multiplier, MATLAB, 4:2 compressor, Adiabatic MTJ/CMOS hybrid structure, ADS.,
Abstract :
The performance of digital signal processors (DSPs) can be improved by introducing some acceptable errors, such as the inaccuracy of hardware computational blocks. In fault-tolerant signal and image processing, approximation multipliers are used. These programs are superior in speed and energy efficiency but sacrifice accuracy. In this paper, we focus on the design of a 4:2 approximation compressor, which is at the heart of the inexact multipliers. This study proposes a concept for an approximation multiplier that uses an MTJ-based 4:2 approximation compressor to reduce hardware and power consumption compared to current designs. Using 180 nm CMOS technology and a novel adiabatic MTJ/CMOS hybrid structure, a method is proposed to create compressor circuits with a 4:2 approximation compressor. The evaluation findings in the above-mentioned technology show a significant improvement in the proposed system. The compressor performance was simulated in ADS and calculated in terms of delay, power and power delay product (PDP) with values of 969.53 µj, 067.41 ps and 216.2 fsj, respectively. When multiplying images in MATLAB, the proposed compressor is used to simulate an 8×8 multiplier. The MSSIM and PSNR are competitive with values of 26.79 and 15.52, respectively, which is comparable to more complex approximation coefficients.
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