معرفی یک معماری جدید CMOS-MTJ برای کمپرسورهای تقریبی 4:2 سریع و کم¬توان: بررسی کاربردهای آنها در پردازش تصویر
الموضوعات :
1 - دانشگاه ازاد اسلامی واحد یزد
الکلمات المفتاحية: ضرب¬کننده تقریبی, متلب, کمپرسور 4:2, ساختار هیبریدی آدیاباتیک MTJ/CMOS, ADS,
ملخص المقالة :
عملکرد پردازندههای سیگنال دیجیتال را میتوان با اعمال برخی خطاهای قابل قبول، مانند عدم دقت بلوکهای محاسباتی سختافزاری، بهبود بخشید. در پردازش سیگنال و تصویر مقاوم به خطا، از ضریبهای تقریبی استفاده میشود. این برنامهها در سرعت و بهرهوری انرژی برتر هستند اما دقت را قربانی میکنند. در این مقاله، ما بر روی طراحی یک کمپرسور تقریبی 4:2 تمرکز میکنیم که در قلب ضربهای غیردقیق قرار دارد. این مطالعه مفهومی را برای یک ضریب تقریبی پیشنهاد میکند که از یک کمپرسور تقریبی 4:2 بر اساس MTJ به منظور کاهش سختافزار و مصرف برق استفاده میکند. با استفاده از فناوری CMOS 180 نانومتری و ساختار هیبریدی MTJ/CMOS آدیاباتیک جدید، روشی برای ایجاد مدارهای کمپرسور با کمپرسور تقریبی 4:2 پیشنهاد شده است. یافتههای ارزیابی در فناوری ذکر شده در بالا، بهبود قابل توجهی را در سیستم پیشنهادی نشان میدهد. عملکرد کمپرسور در ADS شبیهسازی شد و از نظر تاخیر، توان و محصول تاخیر توان با مقادیر 969/53 µj و 067/41ps و 216/2 fsj به ترتیب محاسبه شد. هنگام ضرب تصاویر در متلب، از کمپرسور پیشنهادی برای شبیهسازی یک ضربکننده ۸×۸ استفاده میشود. شاخصهای MSSIM و PSNR با مقادیر 26/79و 15/52 این ضریب با ضریبهای تقریبی پیچیدهتر قابل رقابت هستند.
[1] R. Reis, Y. Cao, and G. Wirth, Circuit design for reliability: Springer, 2015. https://doi.org/10.1007/978-1-4614-4078-9
[2] S. Mittal, "A survey of techniques for approximate computing," ACM Computing Surveys (CSUR), vol. 48, pp. 1-33, 2016. https://doi.org/10.1145/2893356
[3] M. Pedram and J. M. Rabaey, Power aware design methodologies: Springer Science & Business Media, 2002. https://doi.org/10.1007/b101914
[4] Y. Zhang, W. Zhao, J.-O. Klein, W. Kang, D. Querlioz, Y. Zhang, et al., "Spintronics for low-power computing," in 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, pp. 1-6.
[5] W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzanis, and E. Y.-C. Chou, "Low-power digital systems based on adiabatic-switching principles," IEEE Transactions on very large scale integration (VLSI) systems, vol. 2, pp. 398-407, 1994. DOI: 10.1109/92.335009
[6] S. Matsunaga, J. Hayakawa, S. Ikeda, K. Miura, H. Hasegawa, T. Endoh, et al., "Fabrication of a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions," Applied Physics Express, vol. 1, p. 091301, 2008. DOI:10.1143/APEX.1.091301
[7] E. Deng, Y. Zhang, J.-O. Klein, D. Ravelsona, C. Chappert, and W. Zhao, "Low power magnetic full-adder based on spin transfer torque MRAM," IEEE transactions on magnetics, vol. 49, pp. 4982-4987, 2013. DOI: 10.1109/TMAG.2013.2245911
[8] S. Venkataramani, S. T. Chakradhar, K. Roy, and A. Raghunathan, "Approximate computing and the quest for computing efficiency," in Proceedings of the 52nd Annual Design Automation Conference, 2015, pp. 1-6. https://doi.org/10.1145/2744769.275116
[9] B. K. Mohanty and A. Choubey, "Efficient design for radix-8 booth multiplier and its application in lifting 2-D DWT," Circuits, Systems, and Signal Processing, vol. 36, pp. 1129-1149, 2017. https://doi.org/10.1007/s00034-016-0349-9
[10] S. Tabrizchi, N. Azimi, and N. Keivan, "Design a novel ternary half adder and multiplier based on carbon nano-tube field effect transistors (CNTFETs)," Frontiers, vol. 1, pp. 423-433, 2016. https://doi.org/10.1631/FITEE.1500366
[11] P. Aliparast, Z. D. Koozehkanani, and F. Nazari, "An ultra high speed digital 4-2 compressor in 65-nm CMOS," International Journal of Computer Theory and Engineering, vol. 5, p. 593, 2013. DOI: 10.7763/IJCTE.2013.V5.756
[12] F. Sharifi, Z. Saifullah, and A.-H. Badawy, "Design of adiabatic MTJ-CMOS hybrid circuits," in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, pp. 715-718. DOI: 10.1109/MWSCAS.2017.8053023
[13] M. Ahmadinejad and M. H. Moaiyeri, "Energy-efficient magnetic 5: 2 compressors based on SHE-assisted hybrid MTJ/FinFET logic," Journal of Computational Electronics, vol. 19, pp. 206-221, 2020. DOI: 10.1007/s10825-019-01441-0
[14] M. Maleknejad, S. M. Mirhosseini, and S. Mohammadi, "A CNFET-based PVT-tolerant hybrid majority logic 4: 2 compressor design for high speed energy-efficient applications," Microprocessors and Microsystems, p. 104031, 2021. https://doi.org/10.1016/j.micpro.2021.104031
[15] L. Maddisetti, R. K. Senapati, and J. Ravindra, "Accuracy evaluation of a trained neural network by energy efficient approximate 4: 2 compressor," Computers & Electrical Engineering, vol. 92, p. 107137, 2021. https://doi.org/10.1016/j.compeleceng.2021.107137
[16] B. Fang, H. Liang, D. Xu, M. Yi, Y. Sheng, C. Jiang, et al., "Approximate multipliers based on a novel unbiased approximate 4-2 compressor," Integration, vol. 81, pp. 17-24, 2021. https://doi.org/10.1016/j.vlsi.2021.05.003
[17] M. M. D. Savio, T. Deepa, P. D. Dharshini, K. Sonali, and O. Singh, "Design of High speed Multiplier using Input Scrambled 5-3 compressor for Error Tolerant image processing," in Journal of Physics: Conference Series, 2022, p. 012044. DOI: 10.1088/1742-6596/2335/1/012044
[18] R. G. Shankar and D. Ananthi, "Approximate Booth Multipliers using Compressors and Counter," in 2023 International Conference on Inventive Computation Technologies (ICICT), 2023, pp. 1658-1662. DOI: 10.1109/ICICT57646.2023.10134198
[19] P. J. Edavoor, S. Raveendran, and A. D. Rahulkar, "Approximate multiplier design using novel dual-stage 4: 2 compressors," IEEE Access, vol. 8, pp. 48337-48351, 2020. DOI: 10.1109/ACCESS.2020.2978773
[20] N. Srinivas and Y. R. Rao, "Design of High Speed 5: 2 Compressor for Fast Arithmetic Circuits," International Journal of Engineering and Advanced Technology (IJEAT), vol. 6, 2017.
[21] K. M. Reddy, M. Vasantha, Y. N. Kumar, and D. Dwivedi, "Design and analysis of multiplier using approximate 4-2 compressor," AEU-International Journal of Electronics and Communications, vol. 107, pp. 89-97, 2019. https://doi.org/10.1016/j.aeue.2019.05.021
[22] J. S. Moodera, L. R. Kinder, T. M. Wong, and R. Meservey, "Large magnetoresistance at room temperature in ferromagnetic thin film tunnel junctions," Physical review letters, vol. 74, p. 3273, 1995. https://doi.org/10.1103/PhysRevLett.74.3273
[23] R. Zand, A. Roohi, S. Salehi, and R. F. DeMara, "Scalable adaptive spintronic reconfigurable logic using area-matched MTJ design," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, pp. 678-682, 2016. DOI: 10.1109/TCSII.2016.2532099
[24] B. Behin-Aein, J.-P. Wang, and R. Wiesendanger, "Computing with spins and magnets," MRS Bulletin, vol. 39, pp. 696-702, 2014. https://doi.org/10.48550/arXiv.1411.6960
[25] W. Zhao, E. Belhaire, C. Chappert, and P. Mazoyer, "Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit," ACM Transactions on Embedded Computing Systems (TECS), vol. 9, pp. 1-16, 2009. https://doi.org/10.1145/1596543.1596548
[26] R. K. Yadav, A. K. Rana, S. Chauhan, D. Ranka, and K. Yadav, "Adiabatic technique for energy efficient logic circuits design," in 2011 International Conference on Emerging Trends in Electrical and Computer Technology, 2011, pp. 776-780. DOI:10.1109/ICETECT.2011.5760223
[27] P. Hasini and T. K. Murthy, "A Novel high-speed transistorized 8x8 Multiplier using 4-2 Compressors," International Journal of Engineering Research and General Science, vol. 3, pp. 359-365, 2015.
[28] [H. Qi, Y.-B. Kim, and M. Choi, "A high speed low power modulo 2 n+ 1 multiplier design using carbon-nanotube technology," in 2012 IEEE 55th international midwest symposium on circuits and systems (MWSCAS), 2012, pp. 406-409. DOI: 10.1109/MWSCAS.2012.6292043
[29] C.-H. Chang, J. Gu, and M. Zhang, "Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, pp. 1985-1997, 2004. DOI: 10.1109/TCSI.2004.835683
[30] E. Deng, Y. Zhang, J.-O. Klein, D. Ravelsona, C. Chappert, and W. Zhao, "Low power magnetic full-adder based on spin transfer torque MRAM," IEEE transactions on magnetics, vol. 49, pp. 4982-4987, 2013. DOI: 10.1109/TMAG.2013.2245911
[31] F. Sabetzadeh, M. H. Moaiyeri, and M. Ahmadinejad, "A majority-based imprecise multiplier for ultra-efficient approximate image multiplication," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, pp. 4200-4208, 2019. DOI: 10.1109/tcsi.2019.2918241
[32] O. Akbari, M. Kamal, A. Afzali-Kusha, and M. Pedram, "Dual-quality 4: 2 compressors for utilizing in dynamic accuracy configurable multipliers," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, pp. 1352-1361, 2017. DOI: 10.1109/TVLSI.2016.2643003
[33] A. G. M. Strollo, E. Napoli, D. De Caro, N. Petra, and G. Di Meo, "Comparison and extension of approximate 4-2 compressors for low-power approximate multipliers," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, pp. 3021-3034, 2020. DOI: 10.1109/TCSI.2020.2988353
[34] Z. Wang, A. C. Bovik, H. R. Sheikh, and E. P. Simoncelli, "Image quality assessment: from error visibility to structural similarity," IEEE transactions on image processing, vol. 13, pp. 600-612, 2004. DOI: 10.1109/TIP.2003.819861
[35] U. SIPI, "The USC-SIPI image database," ed, 2016.
[36] D. Esposito, A. G. M. Strollo, E. Napoli, D. De Caro, and N. Petra, "Approximate multipliers based on new approximate compressors," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, pp. 4169-4182, 2018. DOI: 10.1109/TCSI.2018.2839266
[37] Y. J. Chang, Y. C. Cheng, Y. F. Lin, S. C. Liao, C. H. Lai, and T. C. Wu, "Imprecise 4‐2 compressor design used in image processing applications," IET Circuits, Devices & Systems, vol. 13, pp. 848-856, 2019. DOI: 10.1049/iet-cds.2018.5403
[38] M. Sam Daliri, K. Navi, R. Faghih Mirzaee, S. Sam Daliri, and N. Bagherzadeh, "A new approach for designing compressors with a new hardware‐friendly mathematical method for multi‐input XOR gates," IET Circuits, Devices & Systems, vol. 11, pp. 46-57, 2017. https://doi.org/10.1049/iet-cds.2016.0041