Efficient Adder Cell Using GDI Structure

Subject Areas : Majlesi Journal of Telecommunication Devices

Mansoureh Labafniya ¹ , Mohammadreza Reshadinejhad ² , Shahram Etemadi Broujeni ³

1 - Isfahan University
2 - Faculty of Computer Engineering, University of Isfahan, Isfahan, Iran
3 - Faculty of Computer Engineering, University of Isfahan, Isfahan, Iran

Received: 2018-09-18 Accepted : 2018-10-15 Published : 2018-09-01

Keywords: PDP, GDI, Adder,

Abstract :

Adder block is one of the major block in circuit design. inserting efficient adder block will cause having more efficient final design. In this paper improved GDI based adder will be designed. Proposed GDI based adder is more efficient in delay, performance and PDP. at last an adder/subtractor circuit will be designed.

References:

[1] K Navi, H HosseinSajedi “High-speed full adder based on minority function and bridge style for nanoscale”, INTEGRATION the VLSI journal44 (2011)155–162

[2] V Foroutan , M Taheri , K Navi , A Azizi Mazreah , “Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style”, INTEGRATION, theVLSIjournal 47(2014)48–61

[3] M Shoba , R Nakkeeran, “GDI based full adders for energy efficient arithmetic applications”, Engineering Science and Technology, an International Journal 19 (2016) 485–496

[4] B Batta, M Choragudi, “Energy Efficient Full-adder using GDI Technique”, journal of research in ijrcct, 2012

[5] A. Morgenshtein, I. Shwartz, A. Fish," Full swing Gate Diffusion Input (GDI) logic case study for low power CLA adder design", Integration (Amst) 47 (1) (2014) 62–70

[6] M. Labafniya, M.Eshghi, “An efficient adder/subtracter circuit for one-hot residue number system”, ICEDSA2010, IEEE 2010