Improved Structure Design of a Single Phase Multilevel Inverter with the Aim of Reducing Switching Devices
الموضوعات :
A. Seifi
1
(Mohaghegh Ardabili University, Ardabil, Iran)
M. Hoseinpour
2
(Mohaghegh Ardabili University, Ardabil, Iran)
M. DejamKhoy
3
(Mohaghegh Ardabili University, Ardabil, Iran.)
F. Sedaghati
4
(Mohaghegh Ardabili University, Ardabil, Iran.)
الکلمات المفتاحية: Total Harmonic Distortion (THD), Multi-Level Inverter (MLI), device reduction, classical topology.,
ملخص المقالة :
In this paper, a multilevel inverter has been designed and improved in order to lower the number of switching devices, especially when the number of level of the output power is large. The input to the inverter comes from internal direct current (DC) resources which are interconnected via the power circuit breaker. Compared to the classical topologies and similar designs, the proposed method needs lower number of switching device to provide the same power levels at the output. As a precursor, we have drawn the desired topology for a 9-level power level. The procedure can be completed using switching by a phase shift keying techniques, which in addition, make practical output power with higher number of levels. The proposed topology has been tested against topologies of the power class 1 and/or similar classes, based on the simulations in the MATLAB/Simulink environment. The results of the simulation deemed to be promising for future networks.
[1] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. Franquelo, B. Wu, J. Rodriguez, M. Perez, and J. Leon, “Recent advances and industrial applications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553–2580, Aug. 2010.
[2] G. Buticchi, E. Lorenzani, and G. Franceschini, “A five-level single-phase grid-connected converter for renewable distributed systems,” IEEE Trans.
[3] Ind. Electron., vol. 60, no. 3, pp. 906–918, Mar. 2013.
[4] J. Rodriguez, J.-S. Lai, and F. ZhengPeng, “Multilevel inverters: A survey of topologies, controls, applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002.
[5] S. De, D. Banerjee, K. Siva Kumar, K. Gopakumar, R. Ramchand, and C. Patel, “Multilevel inverters for low-power application,” IET Power Electronics, vol. 4, no. 4, pp. 384–392, Apr. 2011.
[6] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Pérez, “A survey on cascaded multilevel inverters,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2197–2206, Jul. 2010.
[7] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, “Multilevel voltage-source-converter topologies for industrial medium-voltage drives,” IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 2930–2945, Dec. 2007.
[8] L. M. Tolbert and F. Z. Peng, “Multilevel converters as a utility interface for renewable energy systems,” in Proc. IEEE Power Eng. Soc. Summer Meeting, 2000, vol. 2, pp. 1271–1274.
[9] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, “A new multilevel converter topology with reduced number of power electronic components,” IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 655–667, Feb. 2012.
[10] Y. Hinago and H. Koizumi, “A switched-capacitor inverter using series/ parallel conversion with inductive load,” IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 878–887, Feb. 2012.
[11] S.-J. Park, F.-S. Kang, M. H. Lee, and C.-U. Kim, “A new single-phase five-level PWM inverter employing a deadbeat control scheme,” IEEE Trans. Power Electron., vol. 18, no. 3, pp. 831–843, May 2003.
[12] G.-J. Su, “Multilevel DC-link inverter,” IEEE Trans. Ind. Appl., vol. 41, no. 3, pp. 848–854, May/Jun. 2005.
[13] E. Najafi and A. H. M. Yatim, “Design and implementation of a new multilevel inverter topology,” IEEE Trans. Ind. Electron., vol. 59, no. 11, pp. 4148–4154, Nov. 2012.
[14] J. Pereda and J. Dixon, “High-frequency link: A solution for using only one DC source in asymmetric cascaded multilevel inverters,” IEEE Trans. Ind. Electron., vol. 58, no. 9, pp. 3884–3892, Sep. 2011.
[15] T. A. Lipo and M. D. Manjrekar, “Hybrid topology for multilevel power conversion,” U.S. Patent 6 005 788, Dec. 21, 1999.
[16] X. Kou, K. A. Corzine, and Y. L. Familiant, “Full binary combination schema for floating voltage source multilevel inverters,” IEEE Trans. Power Electron., vol. 17, no. 6, pp. 891–897, Nov. 2002.
[17] Y. Ounejjar, K. Al-Haddad, and L. A. Dessaint, “A novel six-band hysteresis control for the packed U cells seven-level converter: Experimental validation,” IEEE Trans. Ind. Electron., vol. 59, no. 10, pp. 3808–3816, Oct. 2012.
[18] C. A. Silva, L. A. Cordova, P. Lezana, and L. Empringham, “Implementation and control of a hybrid multilevel converter with floating DC links for current waveform improvement,” IEEE Trans. Ind. Electron., vol. 58, no. 6, pp. 2304–2312, Jun. 2011.
[19] K. K. Gupta and S. Jain, “Topology for multilevel inverters to attain maximum number of levels from given DC sources,” IET Power Electron., vol. 5, no. 4, pp. 435–446, Apr. 2012.
[20] C.-M. Young, N.-Y. Chu, L.-R. Chen, Y.-C. Hsiao, and C.-Z. Li, “A single-phase multilevel inverter with battery balancing,” IEEE Trans. Ind. Electron., vol. 60, no. 5, pp. 1972–1978, May 2013.
[21] S. Rohner, S. Bernet, M. Hiller, and R. Sommer, “Modulation, losses, semiconductor requirements of modular multilevel converters,” IEEE Trans. Industrial Electronics, vol. 57, no. 8, pp. 2633–2642, Aug. 2010.
[22] M. Ned, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design., 2nd ed. Hoboken, NJ, USA: Wiley, 2001.
[23] P. C. Loh, D. G. Holmes, and T. A. Lipo, “Implementation and control distributed PWM cascaded multilevel inverters with minimal harmonic distortion and common-mode voltage,” IEEE Trans. Power Electron. The vol. 20, no. 1, pp. 90–99, Jan. 2005.
[24] W. Yao, H. Hu, and Z. Lu, “Comparisons of space-vector modulation and carrier-based modulation of multilevel inverter,” IEEE Trans. Power Electron., vol. 23, no. 1, pp. 45–51, Jan. 2008.
[25] Z. Du, L. M. Tolbert, and J. N. Chiasson, “Active harmonic elimination for multilevel converters,”IEEETrans. Power Electron., vol. 21, no. 2, pp. 459–469, Mar. 2006.
[26] V. Blasko, “A novel method for selective harmonic elimination in power electronic equipment,” IEEE Trans. Power Electron., vol. 22, no. 1, pp. 223–228, Jan. 2007.
[27] M. Angulo, P. Lezana, S. Kouro, J.Rodriguez, and B. Wu, “Level-shifted PWM for cascaded multilevel inverters with even power distribution,” in Proc. IEEE Power Electron. Spec. Conf., pp. 2373–2378.
[28] A. Salem, E. M. Ahmad, M. Orabi and M. Ahamd, “New Three-Phase
[29] Phase Symmetrical Multilevel Voltage Source Inverter,” IEEE journal on emerging and selected topics in circuits and systems 5 (3), 430-442, 2015.
[30] A.Ajami, M.R.JannatiOskuee, M.Toopchi Khosroshahi and A.Mokhberdoran, “Cascade-multi-cell multilevel converter with reduced number of switches,” IET Power Electron., Vol. 7, no. 3, pp. 552–558, 2014.
[31] R. S. Alishah, D. Nazarpour, S. H. Hosseini and M. Sabahi, “Switched-diode structure for multilevel converter with reduced number of power electronic devices,” IET Power Electron., Vol. 7, no. 3, pp. 648–656, 2014.
[32] B. Das, A. Bhattacharya, D. Chatterjee and P.R.Kasari, “Development of Modified Cascaded Multilevel Inverter Configuration with Less Number of Switches,” Proc. of the 2017 IEEE Region 10 Conference (TENCON), Malaysia, November 5-8, 2017.
[33] A.Edpuganti and Akshay K. Rathore, “Fundamental Switching Frequency Optimal Pulsewidth Modulation of Medium Voltage Nine-Level (9L) Inverter,” IEEE Transactions on Industrial Electronics, 2014 DOI:10.1109/TIE.2014.2379583.
[34] K. L. Madhav, C.Babu, P.Ponnambalam and A.Mahapatra, “Fuzzy Logic Controller for Nine Level Multi-Level Inverter with Reduced Number of Switches,” power and Advanced CoputingTecgnologies(i-PACT),2017 innovations in, 1-7, 2017.
[35] Sandeep N and Udaykumar R. Yaragatti, “Design and implementation of active neutral-point-clamped nine-level reduced device count inverter: an application to grid integrated renewable energy sources,” IET Power Electron., Vol. 11 no. 1, pp. 82-91, 2018.
[36] C. I. Odeh and D. B. N. Nnadi, “Single-phase 9-level hybridised cascaded multilevel inverter,” IET Power Electron., Vol. 6, Iss. 3, pp. 468–477, 2013.
[37] V.singh, G. v. v. r. babu and V. P. Singh, “New Multi-level Inverter Topology with Reduced Number of Switches, ”Electronics, Communication and Aerospace Technology (ICECA), 2017 International conference of 1, 462-467, 2017.
[38] R. Yadav, P. Bansal and A. R. Saxena, “A Three-Phase 9-Level Inverter with Reduced Switching Devices for Different PWM Techniques,” Power India International Conference (PIICON), 2014 6th IEEE, 1-6, 2014.
