طراحی کارآمد تقسیم کننده غیربازیابی برگشت پذیر با قابلیت حفظ توازن
محمد طالبی
1
(
دانشکده فنی و مهندسی، گروه کامپیوتر، دانشگاه آزاد اسلامی واحد دزفول، دزفول، ایران
)
محمد مصلح
2
(
دانشکده فنی و مهندسی، گروه کامپیوتر، دانشگاه آزاد اسلامی واحددزفول، دزفول، ایران
)
محسن چکین
3
(
دانشکده فنی و مهندسی، گروه کامپیوتر، دانشگاه آزاد اسلامی واحد دزفول، دزفول، ایران
)
کلید واژه: تقسیم کننده, الگوریتم با روش غیربازیابی, محاسبات کوانتومی, منطق برگشت پذیر, مدار برگشت پذیر با قابلیت حفظ توازن ,
چکیده مقاله :
یکی از چالش¬های اساسی در مدارات مجتمع پرتراکم، اتلاف توان مصرفی است که به واسطه وجود ترانزیستورها در مدارات ایجاد می¬شود و موجب می¬گردد دمای مدار افزایش یابد. طراحی مدارات دیجیتال به شیوه برگشتپذیر می¬تواند به عنوان یکی از رویکردهای کارآمد برای رفع این چالش به کار گرفته شود. علاوه بر این، طراحی مدارات برگشتپذیر با قابلیت حفظ توازن می¬تواند در تشخیص اشکالات در مدارات بسیار مؤثر باشد. تقسیم‌کننده¬ها به عنوان یکی از مدارات پرکاربرد در سیستم¬های محاسباتی دیجیتال مورد استفاده قرار می¬گیرند. مدارات تقسیم¬کننده متشکل از واحد¬های پایه¬ای جمع¬کننده، مالتی¬پلکسر و دو مدار ترتیبی ثبات و ثبات شیفت به چپ با قابلیت بار شدن موازی هستند. این مقاله یک طراحی جدید و کارآمد از تقسیم-کننده غیربازیابی برگشت¬پذیر با قابلیت حفظ توازن ارائه می¬کند. برای این منظور در ابتدا یک نگهدارنده حالت نوع D برگشتپذیر با قابلیت حفظ توازن پیشنهاد شده است. سپس یک ثبات n بیتی برگشت¬پذیر با قابلیت حفظ توازن با استفاده از نگهدارنده حالت برگشت¬پذیر پیشنهادی ارائه گردیده است. در ادامه یک شیفت ثبات n+1 بیتی برگشتپذیر با ¬قابلیت حفظ توازن با استفاده از نگهدارنده پیشنهادی و سایر دروازه‌های برگشتپذیر پیشنهاد شده است. در نهایت تقسیم¬کننده برگشت¬پذیر n بیتی با قابلیت حفظ توازن بر اساس الگوریتم غیربازیابی توسعه یافته است. نتایج حاصل از مقایسه¬ها نشان می¬دهند مدار پیشنهادی از لحاظ معیارهای ارزیابی مدارات برگشت¬پذیر همچون هزینه کوانتومی، تعداد ورودی¬های ثابت و تعداد خروجی-های زائد در مقایسه با کارهای پیشین برتری دارند.
چکیده انگلیسی :
One of the basic challenges in high-density integrated circuits is loss of power consumption, which is caused by presence of transistors in circuits and causes the temperature of the circuit to increase. The design of digital circuits in a reversible way can be used as one of efficient approaches to solve this challenge. In addition, the design of parity-preserving reversible circuits can be very effective in detecting faults in circuits. Dividers are used as one of the most widely used circuits in digital computing systems. Divider circuits include an adder, a multiplexer and two sequential register and parallel-in to parallel-out left shift register circuits. This paper is presented a new and efficient design of a parity-preserving reversible non-restoring divider. For this purpose, first, a parity-preserving reversible D-latch is proposed. second, a parity-preserving reversible n-bit register is presented using the proposed reversible D-latch. Third, a parity-preserving reversible (n+1) bit shift register using the proposed reversible D-latch and other reversible gates is proposed. Finally, a parity-preserving reversible n bit divider is developed based on the non-restoring algorithm. The results of comparisons show that the proposed circuit is superior in terms of evaluation criteria of reversible circuits such as quantum cost, number of constant inputs and number of garbage outputs compared to previous works.
پیشنهاد یک حافظه نگهدارنده حالت (D-latch) D برگشتپذیر با قابلیت حفظ توازن
معرفی یک ثبات برگشت پذیر با قابلیت حفظ توازن
ارائه یک ثبات شیفت به چپ با قابلیت بار موازی (PIPO) برگشتپذیر با قابلیت حفظ توازن
توسعه یک تقسیم کننده غیربازیابی برگشت پذیر کارآمد با قابلیت حفظ توازن با استفاده از مدارات پیشنهادی
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