Analysis and Design of a High Performance Radix-4 Booth Scheme in CMOS Technology

Subject Areas : Majlesi Journal of Telecommunication Devices

Ali Rahnamaei ¹

1 - Department of Electrical Engineering, Ardabil Branch, Islamic Azad University, Ardabil, Iran.

Received: 2021-03-14 Accepted : 2021-03-26 Published : 2021-06-01

Keywords: Partial Product, High-Speed, Parallel multiplier, Low power, Radix-4 Booth Algorithm,

Abstract :

In this paper, a novel high performance structure has been demonstrated which can be widely used for circuit-level realization of radix-4 Booth scheme. The notable privilege of proposed scheme is its higher speed for generation of Partial Products (PPs) compared to the previous designs. The objective has been achieved by means of the modified truth table of Booth algorithm. Moreover, Pass-Transistor Logic (PTL) has been employed to reduce the middle stage capacitances which has considerably enhanced the operating frequency of the designed architecture. The thorough analysis over previously reported works has also been provided to help the authors for optimized implementation of the Booth circuitry. Simulation results for TSMC 0.18µm CMOS technology and 1.8V power supply using HSPICE indicate the correct operation of the proposed scheme. In addition, the best-reported works have been redesigned and simulated on the same conditions to provide a fair comparative environment with our designed scheme. The results demonstrate the superiority of our circuit over the selected structures.

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