Reliability Computation for Single Event Transient on Various Encoder Structures of Flash ADCs

Subject Areas : journal of Artificial Intelligence in Electrical Engineering

MOHAMMAD nazaralilou ¹ , behrouz tousi ^{2 *} , Mohammad Farhadi ³

1 - Department of Electrical Engineering, Urmia University, Urmia, Iran
2 - Department of Electrical Engineering, Urmia University, Urmia, Iran
3 - Department of Electrical Engineering, Urmia University, Urmia, Iran

Received: 2024-10-21 Accepted : 2024-12-31 Published : 2025-02-08

Keywords: Reliability, Single Event Transient, Encoder, Flash ADC. ,

Abstract :

the importance of reliability of digital circuits and the impact of cosmic radiation and single event transient (SET) on circuits, with reducing the technology scaling and operating voltage, is increasing dramatically. In this paper, the reliability of different encoder structures that used in the flash analog to digital converters, were calculated and compared in term of single event transient. The impacts of masking (logic and electrical) and crosstalk effects between interconnects on reliability are considered when evaluating the reliability of SET in this circuits. The results indicate that reliability for SET on Encoder Rom structure is more than other structures. The masking and crosstalk effects will improve the reliability of this circuits by more than 42%. 

References:

[1] Marko Andjelkovic, Milos Krstic, “Characterization and modeling of Single Event Transient propagation through standard combinational cells,” Microelectronics Reliability,November 2023, volume 150.
[2] Shuo Cai, Binyong He, Weizheng Wang, Peng Liu, Fei Yu, Lairong Yin, Bo Li, “Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults,” Journal of Electronic Testing, 2020, volume 36, pp. 469–483.
[3] Jahanzeb Anwer, Sebastian Meisner, Marco Platzner, “Dynamic Reliability Management for FPGA-Based Systems,” International Journal of Reconfigurable Computing, June 2020, pp, 1 - 19.
[4] H. H. Lee, K. Lilja, M. Bunasser, I. Linscott, and U. Inan, “Single Event Transient on Combinational Logic: An Introduction and their Mitigation,” Journal of Integrated Circuits and Systems, vol. 17, n. 3, 2022.
[5] Yaqing Chi, Zhenyu Wu, Pengcheng Huang, Qian Sun, Bin Liang, Zhenyu Zhao, “Characterization of single-event transients induced by high LET heavy ions in 16 nm bulk FinFET inverter chains,” Microelectronics Reliability, Volume 130, March 2022, 114490.
[6] Marko S. Andjelković, “A methodology for characterization, modeling and mitigation of single event transient effects in CMOS standard combinational cells,” Thesis, Apr 2022.
[7] B. Liu and L. Cai, “Reliability Evolution for Single Event Transient on Digital Circuit,” IEEE Transaction on Reliability, 61(3), 2012, pp. 592 – 601.
[8] Daisuke Kobayashi, “Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison with Transistor Performance,” IEEE Transactions on Nuclear Science, December 2020, PP (99):1-1.
[9] G. Levitin and L. xing, “Reliability and performance of multistate systems with propagated failures having selective effect,” Reliability Engineering and system safety, vol. 95, 2010, pp.655-661.
[10] Krishnaswamy, S., Viamontes, G.F., Markov, I.L. and Hayes, J.P., "Probabilistic transfer matrices in symbolic reliability analysis of logic circuits," ACM Trans. Design Automation of Electronic Systems, 13, no. 1, pp.8:1-8:35, Jan. 2008.
[11] Ghaith bany hamad, Otmane Ait Mohamed, Yvon Savaria, “ Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits,” Journal of Electronic Testing, October 2017, pp. 33(1).

Full-Text:



M. Nazaralilou, B. Tousi , M.Farhadi-kangarlu: Reliability Computation for Single Event …

 

Reliability Computation for Single Event Transient on Various Encoder Structures of Flash ADCs

Mohammad Nazaralilou1, Behrouz Tousi2*, Mohammad Farhadi-kangarlu3

1,2,3Department of Electrical Engineering, Urmia University, Urmia, Iran

Email:[e-mail],  [e-mail]( Corresponding Author),   [e-mail],ir

Receive Date: 21 Oct 2024     Revise Date: 28 Nov 2024        Accept Date:31 Dec 2024

Abstract

The importance of reliability of digital circuits and the impact of cosmic radiation and single event transient (SET) on circuits, with reducing the technology scaling and operating voltage, is increasing dramatically. In this paper, the reliability of different encoder structures that used in the flash analog to digital converters, were calculated and compared in term of single event transient. The impacts of masking (logic and electrical) and crosstalk effects between interconnects on reliability are considered when evaluating the reliability of SET in this circuits. The results indicate that reliability for SET on Encoder Rom structure is more than other structures. The masking and crosstalk effects will improve the reliability of this circuits by more than 42%.

Keywords: Reliability, Single Event Transient, Encoder, Flash ADC

 

1.       Introduction

In terms of reliability, application of systems divided into two types named critical and non-critical. Obviously, in critical applications, reliability is essential requirement. Today, advances in technology have made the Reliability for non-critical applications is also considered important. The reason is that, the numerous incidence of errors in a system causes the loss of credibility manufacturer and market future products is at risk. Therefore, today the reliability for all applications, including critical and noncritical, is an important parameter [1], [2]. Failure of submicron technology-based circuits can be divided into two parts permanently failures and temporary failures. Among these, failures caused by the collision of energetic particles emitted by cosmic rays and alpha particles into sensitive areas of a semiconductors material, because of the density and distribution of energy, is of particular importance. When a high-energy particles strike the sensitive part of a semiconductor material, a dense channel of electrons and holes is created. The presence of an electric field causes the current carriers moving in the circuit and if they can charge or discharge a capacitor in the hit node, transient voltage pulse is created. If the content of memory element impressed during this operation and its logic is changed, the so-called soft error has occurred. It is reported that in a favorable environment, 90% of failures in a computer system caused by transient failures [3]. For this reason, in assessing the reliability and system failure, transient failure are more important. In general, there is the possibility of collision of energetic particles with different components of a digital circuit including logic, memory elements and the control signal lines. Figure 1 shows different parts of the circuit and different modes of influence of particle collisions. Particle collision to a logic gates produce and inject charge that after passing through the logic circuits, Cause transient voltage ripple occurs at the output of the combination part that named single event transient(SET). These SETs during transmission and spread, Can be masked by logical and electrical structure or latch sampling period and Prevent to be further transmission and spread. These three factors are somewhat reduce probability of soft error. But still a large number of transient wave with a sufficient period of time to be reach the storage elements and Leading to the occurrence of breakdowns and software errors. Particle collisions can directly affect the internal nodes of the memory circuits and leading to the change of status of circuit. This phenomenon is called single event upset (SEU) [4]. Particle collisions with controlling circuits, such as clock pulse circuits could enable control signals faulty and thus save the unwanted data [5].

The effect of SETs on the reliability of digital systems under radiation should be considered by designers who exploit deep submicron technologies [6], [11]. Available, accurate methods for calculating the impact of SET on IC designs are thus needed [6]. However, there are few related works for calculating the reliability of SETs in logic circuits.

Baojun Liu et al. proposed an algorithm for evaluating the reliability of single event transients on digital ICs. The algorithm is based on defined multi-state systems, and signal probability. The impacts of masking (logic and electrical) and crosstalk effects between interconnects on reliability are considered when evaluating the reliability of SET in logic circuits [7].

This paper gives the importance of digital system reliability, calculate and compare the reliability of different encoder structures that are used in the flash analog to digital converters, in terms of single event transient. The rest of the paper is organized as follows. In Section II, conventional method for reliability evaluation is presented. In Section III, reliability evaluation for SETs on various encoder structures of flash ADCs are presented. Section IV presents analysis and simulation results. Section V concludes this paper.

2.       The conventional method used to calculate the reliability of digital circuits

A.       Reliability Evaluation Based on Universal Generating Function and Multi-State Model of SETs

In this paper, the proposed method in [7] is used to reliability analysis of various encoders. First, the multistate of SETs pulses were defined, as shown in Fig. 2 (table 1).

So any signal line may spread a multi-state signal, illustrated by the set S= {0, a, b,, 1}. When a SET occurs at node in a digital circuit, extracted are all on-path signals and gates from to every reachable primary out put.This result can be achieved using the forward Depth-First-Search (DFS) algorithm [8].

 

 

Fig. 1. The effect of particle collisions in different parts of the circuit

 

 

Fig. 2.  Status of SETs signal

        

Table1-Definition of SETs signal

 

 

Table 2- Mapping function of main gates.

Signal Status	Quantity
0	No SET is propagated to this signal line, and it has an error-free value of 0.
1	No SET is propagated to this signal line, and it has an error-free value of 1.
a	Signal propagate a SET from logic 0, and the maximum value of it is less than 0.5 (VDD*/2).
	Signal propagate a SET from logic 1, and the minimum value of it is more than 0.5.
b	Signal propagate a SET from logic 0, and the maximum value of it is more than 0.5.
	Signal propagate a SET from logic 1, and the minimum value of it is less than 0.5.

 

 

 

The reliability of SET in the primary output can be expressed as [9].

Gate	Defined Function f
AND
OR
NOT
XOR

Where is the probability mass function of primary outputs and  is an acceptability function which represents the desired relation between the primary output W and some limit values named acceptable range (π(W,θ)=1 if primary output is acceptable and π(W,θ)=0 otherwise). The reliability for SETs from node on digital circuits with k outputs are calculated as.

 

(1)

The universal generating function (u-function), representing the probability mass function of signals, can be defined as [9].

(2)

To obtain the u-function representing the probability mass function of the gate, which consists of signal inputs of, the following defined operator (9) is used [7].

(3)

(4)

From (9), we can find that the key of the u-function calculation is the mapping function. By considering logic masking, we define the mapping function of main gates (including

AND, OR, and NOT) under SETs, as shown in Table 2[7].

B.       Reliability evaluation consideringeffects of masking and crosstalk

It was clear that, gate position and size affection error propagation and logic masking [10]. When a noise disturbance inputs into a gate, the gate can filter and attenuate the disturbance [11]. This phenomenon is called electrical masking. This effect will attenuate the amplitude of the SET noise. Assume that the electrical masking ratio is. If the original u-function of a gate without considering electrical masking is expressed as [7]

Where

(5)

Then the u-function of the gate considering electrical masking effects can be achieved by:

 

(6)

(7)

 

With advances in technology scaling, coupling effects among interconnects, called crosstalk effects, will significantly affect the SETs [9]. Here we only consider the crosstalk effects between interconnects of the inputs of the same gate. Assume that the crosstalk probability is.For a gate with two inputs, the u-function for the signals of the input can be written as [7]

 

(8)

Where

 

 

 

For, because of the crosstalk effects, the probability mass function of it is modified by (16)

 

(9)

Similarly, we can obtain the modifiedconsidering crosstalk effects.

 

 

 

Table 4. Truth Table of 3-bit Gray Code Encoder

(10)

 

3.       Reliability Evaluation for SETs on Various Encoder Structures of Flash ADCs

Fig. 3 shows the general structure of a 3-bit flash ADC. Which consists of a number of comparators which each compares the input signal with a reference signal. The output of comparators are connected to the inputs of an encoder that generates a binary output. In this section three different encoder structures that used in the flash ADCs are introduced and the reliability evolution of these encoders, in terms of single event transient is proposed. For reliability evolution of these circuits we use the algorithm presented in [7].

A.       Gray Code Encoder

Figure 4. Shows structure of gray code encoder for 2 and 3-bit flash ADC. Assume that an SET occurs at intermediate node (G1). Without considering effects of error attenuation and crosstalk, we first constitute the truth table of the 2-bit encoder circuit, shown in Table 3. We next define an on-path gate as a gate on a path from the SET-occurred node to a reachable output. By using the DFS algorithm [8], extract all on-path gates from SET-occurred node (G1) to every reachable primary output.

The probability of status “a” is 0.3, and the probability of “b” is 0.7for the original status “0”; or else the probability of “” is 0.3, and the probability of “” is 0.7 for the status “1”. For any combination S, determine the u-function of the signal of the primary output, and the u-function of the signal probability of other off-path SET signals, as follow. For combination S0 and S3 we have

 

0	0	0	0	0	0	0	0	0	0	0	0	0
1	0	0	1	0	0	1	0	0	0	0	0	0
0	1	0	1	1	0	1	1	0	0	0	0	0
1	1	0	0	1	0	1	1	1	0	0	0	0
0	0	1	0	1	1	1	1	1	1	0	0	0
1	0	1	1	1	1	1	1	1	1	1	0	0
0	1	1	1	0	1	1	1	1	1	1	1	0
1	1	1	0	0	1	1	1	1	1	1	1	1

For combination S1 and S2           Fig. 3. General structure of a 3-bit flash ADC.     Table 3 -Truth Table of 2-bit Gray Code Encoder                   0 0 0 0 0 0 0   1 0 1 0 1 0 0   0 1 1 1 1 1 0   1 1 0 1 1 1 1     Fig. 4. Structure of gray code encoder for 2 (a) and 3-bit (b) flash ADC.   The acceptability function can be defined as Table 4 . Truth table of 3-bit gray code encoder                             0 0 0 0 0 0 0 0 0 0 0 0 0   1 0 0 1 0 0 1 0 0 0 0 0 0   0 1 0 1 1 0 1 1 0 0 0 0 0   1 1 0 0 1 0 1 1 1 0 0 0 0   0 0 1 0 1 1 1 1 1 1 0 0 0   1 0 1 1 1 1 1 1 1 1 1 0 0   0 1 1 1 0 1 1 1 1 1 1 1 0   1 1 1 0 0 1 1 1 1 1 1 1 1   Assume that the probability Qs of the combination of inputs is. The reliability for SET can be achieved as     (11)     (12) For reliability evaluation on SET for 3-bit gray code encoder, assuming that an SET occurs at intermediate node (x1).The truth table of the 3-bit gray code encoder circuit, shown in Table 4. For any combination S, we calculate the u-function of primary output, and signal probability of off-path SET signals. For combination S0.   According to truth table 4 equation 18 is also true for combinations S3, S4, S5, S6and S7. For combination S­1 and S2 we have.             (13) Assume that the probability Qs of the combination of inputs is. The reliability for SET can be achieved as               (14) B.       XOR Based Encoder   Figure 5. Shows structure of XOR based encoder for 2 and 3-bit flash ADC.The truth table of the 2-bit XOR encoder circuit, shown in Table 5. With all previous assumptions, we calculate the reliability for SET for this type of encoder. The u-function for primary output (B1) for combinations S0, S2 and S3 is calculated as follows. Table 5- Truth Table of 2-bit XOR BASED Encoder                 0 0 0 0 0 0   1 0 1 1 0 0   0 1 0 1 1 0   1 1 0 1 1 1   And for combination S1 we have       (15)         The overall reliability is calculated as follows.   Fig. 5. Structure of XOR based encoder for 2 (a) and 3-bit (b) flash ADC.     Fig. 6. Structure of encoder ROM for 2 (a) and 3-bit (b) flash ADC.         (16) For reliability evaluation on SET for 3-bit XOR encoder, assuming that an SET occurs at intermediate node (x1). The truth table of the 3-bit XOR encoder circuit, shown in Table 6. For any combination S, we calculate the u-function of primary output, and signal probability of off-path SET signals. For combination S0.   Table 6- Truth Table of 3-bit XOR BASED Encoder   Table 7 Truth Table of 2-bit Encoder ROM                       0 0 0 0 0 0 0 0 0 0   1 0 0 1 0 0 0 0 0 0   0 1 0 1 1 0 0 0 0 0   1 1 0 1 1 1 0 0 0 0   0 0 1 1 1 1 1 0 0 0   1 0 1 1 1 1 1 1 0 0   0 1 1 1 1 1 1 1 1 0   1 1 1 1 1 1 1 1 1 1                       0 0 0 0 0 0 0 0   1 0 1 0 0 1 0 0   0 1 0 1 0 1 1 0   1 1 0 0 1 1 1 1   According to truth table 6 equation 22 is also true for combinations S3, S4, S5, S6and S7.For combination S1 and S2 we have         (17) Assume that the probability Qs of the combination of inputs is. The reliability for SET can be achieved as         (18)     (19) C.       Encoder ROM Figure 6. Shows structure of encoder ROM circuit for 2 and 3-bit flash ADC. The truth table of the 2-bit encoder ROM circuit, shown in Table 7. Assume that an SET occurs at intermediate node (T ́1). With all previous assumptions, we calculate the reliability for SET for this type of encoder. The u-function for primary output (B1) for S0, S2 and S3 combinations is calculated as follows.         For combination S1 we have Table 8 Truth Table of 3-bit Encoder ROM   Table 9. Reliability of various Encoder Circuits                                     0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0   1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0   0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0   1 1 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0   0 0 1 0 0 0 1 0 0 0 1 1 1 1 0 0 0   1 0 1 0 0 0 0 1 0 0 1 1 1 1 1 0 0   0 1 1 0 0 0 0 0 1 0 1 1 1 1 1 1 0   1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1     Reliability (masking and crosstalk effects) Reliability (only masking effect) Reliability (no effect) Encoder Structure       2-Bit Gray Code Encoder       2-Bit XOR Encoder       2-bit Encoder ROM       3-Bit Gray Code Encoder       3-Bit XOR Encoder       3-bit Encoder ROM       The overall reliability is calculated as follows     (20) For reliability evaluation on SET for 3-bit XOR encoder, assuming that an SET occurs at intermediate node (T ́1). The truth table of the 3-bit XOR encoder circuit, shown in Table 8. For any combination S, we calculate the u-function of primary output, and signal probability of off-path SET signals. For combination S0we have   According to truth table 8 equation 26 is also true for combinations S2, S3, S4, S5, S6 and S7. For combination S1 we have           (21) Assume that the probability Qs of the combination of inputs is . The reliability for SET can be achieved as.           (22)   4-       SIMULATION AND ANALYSIS Assume that probability of weak SET (a,) is 0.3, and the probability of strong SET (b,) is 0.7 at the SET-occur node, the reliabilities of SET in the various 2-bit and 3-bit encoder circuits are evaluated early without considering logic masking and crosstalk effect. Then, assuming an SET occur in the input of presented circuits and electrical masking ratio is 0.7; the crosstalk probability is 0.9; reliability is same again considering the effects of masking and crosstalk for 2 and 3-bit encoders are calculated in different structures. The results are shown in Table 9. From this table it can be resulted that the reliability of Encoder Ram is approximately twice more than other structures. After considering the masking effects, reliability is improved strongly by an average 42.8%. Because of the masking effect alleviate the amplitude of the pulse disturbance. Also compared with the reliability without effect, crosstalk effect and error attenuation of the gates improves reliability on average about 44.5%. 5-       CONCLUSION With advances in fabrication technology and reducing the feature size, single event transients (SETs), is among the most important considerations in the design of digital circuits. Based on multistate model of single event transients and universal generating function, Reliability of three different 2 and 3-bit encoder structures that are used in flash ADCs, is calculated. The results shows that the reliability of Encoder Rom structure is higher than other structures. Also calculates the reliability for 2 and 3-bit encoders in the different structures with respect the logic masking and crosstalk effect indicates the reliability improving strongly. Therefor results of this paper can provide important suggestions for integrated circuits designers and researchers to use structures with high reliability. References [1]       Marko Andjelkovic, Milos Krstic,“Characterization and modeling of Single Event Transient propagation through standard combinational cells,” microelectronicsreliability,November2023, volume 150. [2]       ShuoCai, Binyong He, Weizheng Wang, Peng Liu, Fei Yu, Lairong Yin, Bo Li,“Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults,” Journal of Electronic Testing, 2020, volume 36, pp. 469–483. [3]       ahanzebAnwer, Sebastian Meisner, Marco Platzner, “Dynamic Reliability Management for FPGA-Based Systems,” International Journal of Reconfigurable Computing, June 2020, pp, 1 - 19. [4]       H. H. Lee, K. Lilja, M. Bunasser, I. Linscott, and U. Inan, “Single Event Transient on Combinational Logic: An Introduction and their Mitigation,” Journal of Integrated Circuits and Systems, vol. 17, n. 3, 2022. [5]       Yaqing Chi, Zhenyu Wu, Pengcheng Huang, Qian Sun, Bin Liang, Zhenyu Zhao, “Characterization of single-event transients induced by high LET heavy ions in 16 nm bulk FinFET inverter chains,” Microelectronics Reliability, Volume 130, March 2022, 114490. [6]       Marko S. Andjelković, “A methodology for characterization, modeling and mitigation of single event transient effects in CMOS standard combinational cells,” Thesis, Apr 2022. [7]       B. Liu and L. Cai, “Reliability Evolution for Single Event Transient on Digital Circuit,” IEEE Transaction on Reliability, 61(3), 2012, pp. 592 – 601. [8]       Daisuke Kobayashi, “Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison with Transistor Performance,” IEEE Transactions on Nuclear Science,December 2020, PP (99):1-1. [9]       G. Levitin and L. xing, “Reliability and performance of multistate systems with propagated failures having selective effect,” Reliability Engineering and system safety, vol. 95, 2010, pp.655-661. [10]        +    (23) TABLE 9 Reliability of various Encoder Circuits   Krishnaswamy, S., Viamontes, G.F., Markov, I.L. and Hayes, J.P., "Probabilistic transfer matrices in symbolic reliability analysis of logic circuits," ACM Trans. Design Automation of Electronic Systems, 13, no. 1, pp.8:1-8:35, Jan. 2008. [11]       Ghaithbanyhamad, OtmaneAit Mohamed, YvonSavaria,“Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits,” Journal of Electronic Testing, October 2017, pp. 33(1).     41