A Review of Optical Routers in Photonic Networks-on-Chip: A Literature Survey

Subject Areas : System Integration

Negin Bagheri Renani ¹ , Elham Yaghoubi ²

1 - Computer Engineering Faculty, Najafabad Branch, Islamic Azad University, Najafabad, Iran
2 - Computer Engineering Faculty , Najafabad Branch, Islamic Azad University, Najafabad, Iran

Received: 2018-06-19 Accepted : 2018-09-03 Published : 2018-08-01

Keywords: routing algorithm, Mach-Zehnder Interferometer, Micro Ring Resonator, Optical Network on Chip, Optical Router, waveguide crossing,

Abstract :

Due to the increasing growth of processing cores in complex computational systems, all the connection converted bottleneck for all systems. With the protection of progressing and constructing complex photonic connection on chip, optical data transmission is the best choice for replacing with electrical interconnection for the reason of gathering connection with a high bandwidth and insertion loss on chip was mentioned. Optical routers play an important role in the Optical Network-on-Chip (ONoC), which are responsible for selecting the path between optical signal source and the destination. In recent years, silicon optical routers based on Micro-Ring Resonators (MRRs) and Mach-Zehnder Interferometers (MZIs) have been proposed. The design of optical switches is desirable by using of Mach-Zehnder Interferometer. This is while that Micro Ring Resonator Switches have low bandwidth, whereas Mach-Zehnder Interferometer switches have wide bandwidth inherently. Mach-Zehnder Interferometer switches are able to routing with high speed for data transmission with Nano second switching time. This is while, that MRR switches in compare to MZIs has the less power consumption and area consumption. On the other hand we can divide optical routers into parts, A. general router and B. specific- router, so that in specific routers, some of I/O paths for the reason of avoiding deadlock had be omitted. In continue, several kinds of optical router based on MZI and MRR along with researching a series of parameters was mentioned.

References:

[1]    L. Benini and G. De Micheli, "Networks on chips: A new SoC paradigm," computer, vol. 35, pp. 70-78, 2002.
[2]    K. Bergman, L. P. Carloni, A. Biberman, J. Chan, and G. Hendry, Photonic network-on-chip design: Springer, 2016.
[3]    H. Shabani, A. Roohi, A. Reza, H. Khademolhosseini, and M. Reshadi, "Parallel-XY: A Novel Loss-Aware Non-Blocking Photonic Router for Silicon Nano-Photonic Networks-on-Chip," Journal of Computational and Theoretical Nanoscience, vol. 10, pp. 1510-1514, // 2013.
[4]    E. Yaghoubi and M. Reshadi, "Five-Port Optical Router Design Based on Mach–Zehnder Switches for Photonic Networks-on-Chip," Journal of Advances in Computer Research, vol. 7, pp. 47-53, 2016.
[5]    B. Asadi, M. Reshadi, and A. Khademzadeh, "A routing algorithm for reducing optical loss in photonic Networks-on-Chip," Photonic Network Communications, vol. 34, pp. 52-62, 2017.
[6]    N. E. Jerger and L.-S. Peh, "On-chip networks," Synthesis Lectures on Computer Architecture, vol. 4, pp. 1-141, 2009.
[7]    A. Biberman and K. Bergman, "Optical interconnection networks for high-performance computing systems," Reports on Progress in Physics, vol. 75, p. 046402, 2012.
[8]    A. Runge, "FaFNoC: A Fault-tolerant and Bufferless Network-on-chip," Procedia Computer Science, vol. 56, pp. 397-402, 2015.
[9]    Y. Wu, C. Lu, and Y. Chen, "A survey of routing algorithm for mesh Network-on-Chip," Frontiers of Computer Science, vol. 10, pp. 591-601, 2016.
[10]    B. Little, S. Chu, W. Pan, and Y. Kokubun, "Microring resonator arrays for VLSI photonics," IEEE Photonics Technology Letters, vol. 12, pp. 323-325, 2000.
[11]    A. Shacham, K. Bergman, and L. P. Carloni, "On the design of a photonic network-on-chip," in Networks-on-Chip, 2007. NOCS 2007. First International Symposium on, 2007, pp. 53-64.
[12]    A. Shacham, B. G. Lee, A. Biberman, K. Bergman, and L. P. Carloni, "Photonic NoC for DMA communications in chip multiprocessors," in High-Performance Interconnects, 2007. HOTI 2007. 15th Annual IEEE Symposium on, 2007, pp. 29-38.
[13]    S.-J. Chang, C.-Y. Ni, Z. Wang, and Y.-J. Chen, "A compact and low power consumption optical switch based on microrings," IEEE Photonics Technology Letters, vol. 20, pp. 1021-1023, 2008.
[14]    J. Chan, A. Biberman, B. G. Lee, and K. Bergman, "Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications," in Lasers and Electro-Optics Society, 2008. LEOS 2008. 21st Annual Meeting of the IEEE, 2008, pp. 300-301.
[15]    A. W. Poon, F. Xu, and X. Luo, "Cascaded active silicon microresonator array cross-connect circuits for WDM networks-on-chip," in Silicon Photonics III, 2008, p. 689812.
[16]    A. W. Poon, X. Luo, F. Xu, and H. Chen, "Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection," Proceedings of the IEEE, vol. 97, pp. 1216-1238, 2009.
[17]    R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, et al., "Microring-resonator-based four-port optical router for photonic networks-on-chip," Optics express, vol. 19, pp. 18945-18955, 2011.
[18]    L. Yang, R. Ji, L. Zhang, Y. Tian, J. Ding, H. Chen, et al., "Optical routers for photonic networks-on-chip," in Communications and Photonics Conference and Exhibition, 2011. ACP. Asia, 2011, pp. 1-6.
[19]    R. Min, R. Ji, Q. Chen, L. Zhang, and L. Yang, "A Universal Method for Constructing N-Port Nonblocking Optical Router for Photonic Networks-On-Chip," Journal of Lightwave Technology, vol. 30, pp. 3736-3741, 2012.
[20]    E. Yaghoubi, M. Reshadi, and M. Hosseinzadeh, "Mach–Zehnder-based optical router design for photonic networks on chip," Optical Engineering, vol. 54, p. 035102, 2015.
[21]    M. Yang, W. M. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, et al., "Non-blocking 4x4 electro-optic silicon switch for on-chip photonic networks," Optics express, vol. 19, pp. 47-54, 2011.
[22]    H. Shabani, A. Roohi, A. Reza, M. Reshadi, N. Bagherzadeh, and R. F. DeMara, "Loss-aware switch design and non-blocking detection algorithm for intra-chip scale photonic interconnection networks," IEEE Transactions on Computers, vol. 65, pp. 1789-1801, 2016.
[23]    X. Li, X. Xiao, H. Xu, Z. Li, T. Chu, J. Yu, et al., "Mach–Zehnder-based five-port silicon router for optical interconnects," Optics letters, vol. 38, pp. 1703-1705, 2013.
[24]    Q. Chen, F. Zhang, R. Ji, L. Zhang, and L. Yang, "Universal method for constructing N-port non-blocking optical router based on 2× 2 optical switch for photonic networks-on-chip," Optics Express, vol. 22, pp. 12614-12627, 2014.
[25]    M. Geng, Z. Tang, K. Chang, X. Huang, and J. Zheng, "N-port strictly non-blocking optical router based on Mach-Zehnder optical switch for photonic networks-on-chip," Optics Communications, vol. 383, pp. 472-477, 2017/01/15/ 2017.
[26]    H. Gu, J. Xu, and Z. Wang, "A novel optical mesh network-on-chip for gigascale systems-on-chip," in Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on, 2008, pp. 1728-1731.
[27]    G. Hendry, J. Chan, S. Kamil, L. Oliker, J. Shalf, L. P. Carloni, et al., "Silicon nanophotonic network-on-chip using TDM arbitration," in High Performance Interconnects (HOTI), 2010 IEEE 18th Annual Symposium on, 2010, pp. 88-95.