Superior electronic properties of graphene make it a substitute candidate for beyond-CMOS nanoelectronics in electronic devices such as the field-effect transistors (FETs), tunnel barriers, and quantum dots. The armchair-edge graphene nanoribbons (AGNRs), which have semiconductor behavior, are used to design the digital circuits. This paper presents a new design of ternary half adder based on graphene nanoribbon FETs (GNRFETs). Because of reducing chip area and integrated circuit (IC) interconnects, ternary value logic is a good alternative to binary logic. Extensive simulations have been performed in Hspice with 15-nm GNRFET technology to investigate the power consumption and delay. Results show that the proposed design is very high-speed in comparison with carbon nanotube FETs (CNTFETs). The proposed ternary half adder based on GNRFET at 0.9V exhibiting a low power-delay-product (PDP) of ~10-20 J, which is a high improvement in comparison with the ternary circuits based on CNTFET, lately proposed in the literature. This proposed ternary half adder can be advantageous in complex arithmetic circuits. پرونده مقاله

This paper introduces a new design of penternary inverter gate based on graphene nanoribbon field effect transistor (GNRFET). The penternary logic is one of Multiple-valued logic (MVL) circuits which are the best substitute for binary logic because of its low power-delay product (PDP) resulting from reduced complexity of interconnects and chip area. GNRFET is preferred over Si-MOSFET for circuit design due to its fantastic thermal, mechanical and electrical properties. For this circuit design, the voltage divisions obtained with resistors. All the circuits are simulated and compared by HSPICE, 15nm GNR Technology with the supply voltage of 0.8V. Simulation results demonstrate that the PDP is about 1e-18. Therefore, MVL design based on GNRFET leads to minimum PDP than other devices such as CNTFET. Furthermore, the transient wave is absolutely accurate. The variation of the figure of merits (FOM) such as power consumption, propagation delay, and PDP is investigated as a function of a number of the ribbon in GNRFET structure. پرونده مقاله

Due to the high density and the low consumption power in the digital integrated circuits, mostly technology of CMOS is used. During the past times, the Metal oxide silicon field effect transistors (MOSFET) had been used for the design and implementation of the digital integrated circuits because they are compact and also they have the less consumption power and delay to the other transistors. But after discovering the carbon nano-tubes by Ijima et al., several studies have been done on these structures in the other sciences. Single cover nano-tubes due to the electrical traits such as low consumption power, high speed, the compact area with the smallest dimensions in the form of nano by the unique configuration, multiple threshold recognition, least threshold of noise, etc. better than the other nano-tubes. Over the past times, bi-valued logic was used but these days, multi-valued logic (due to the features such as high speed in the transfer of information, decrease of the number of gate, the decrease of operation, etc) is being used. Among the multi-valued logics, triple one because of less evaluated cost of installation and the simple method for implementation of the electronic circuits, is considered more than the other. In this article, by the use of triple-valued field of Galois, the multiplier circuits based on Metal oxide silicon field effect transistors (MOSFET) as well, the transistors of field effect of semi-carbon nano-tubes were designed and implemented. پرونده مقاله