طراحی و شبیه‌سازی یک تقویت‌کننده ترارسانای عملیاتی راه‌اندازی شده از طریق بدنه مبتنی بر فناوری ترانزیستور اثر میدان نانولوله‌کربنی
محورهای موضوعی : انرژی های تجدیدپذیر
سید محمد علی زنجانی
1
(مرکز تحقیقات ریز شبکه های هوشمند- واحد نجف آباد، دانشگاه آزاد اسلامی، نجف آباد، ایران)
مصطفی پرویزی
2
(دانشکده مهندسی برق- واحد نجف آباد، دانشگاه آزاد اسلامی، نجف آباد، ایران)
کلید واژه: توان پایین, تقویت‌کننده ترارسانای عملیاتی, ترانزیستور اثر میان نانولوله‌کربنی, بهره بالا, تکنیک gm/ID,
چکیده مقاله :
در این مقاله، یک مدار تقویت کننده ترارسانایی عملیاتی جدید دو طبقه پیشنهاد می شود که نیاز های بهره بالا، توان مصرفی پایین و نویز کم را برآورده می کند و بر اساس روشgm/ID و راه اندازی از طریق بدنه طراحی شده است. قابل ذکر است که طراحی های صورت گرفته مداری با توجه به محدودیت های فناوری CMOS، در فناوری CNTFET انجام شده است. همچنین به منظور بهبود خطینگی مدار، ترانزیستورهای تریودی در هر دوطبقه به کار برده شده است. شبیه سازی های مدار تقویت کننده ترارسانایی عملیاتی پیشنهادی در نرم افزار HSPICE و با ولتاژ تغذیه یک ولت و خازن های بار یک پیکوفاراد انجام پذیرفته است. بر اساس نتایج به دست آمده، مدار پیشنهادی کمتر از 27 میکرووات توان مصرف می کند و بهره بالای 98 دسی بل را ارائه می دهد. مقدار CMRR و PSRR مدار پیشنهاد شده به ترتیب برابر با 121 دسی بل و 152 دسی بل است. نویز ارجاع شده به ورودی مدار برابر با 92/0 نانو ولت بر رادیکال هرتز بوده و سرعت چرخش مدار برابر با 111 ولت بر میکروثانیه است که نشان از بهتربودن مقدار ضریب شایستگی مدار پیشنهادی در مقایسه با کارهای قبلی است.
In this paper, a new two-stage OTA is proposed which meeting the needs of high gain, low power and low noise, and designed based on the gm/ID technique with bulk driven method. It is noteworthy that due to the limitations of CMOS technology, CNTFET technology used for the circuit designs. Moreover, to improve the linearity of the circuit, triode transistors used in both stages of amplifiers. The simulation results of the proposed OTA are performed under 1V of supply voltage and 1pF of load capacitors in the HSPICE tool. According to the simulation results, the proposed circuit consumes less than 27 µW of power and offers a high gain of 98 dB. The CMRR and PSRR values of the proposed circuit are 121 dB and 152 dB, respectively. The input referred noise is 0.92 nV/√Hz and the slew rate of the proposed circuit is 111 V/µs, which shown the better figure of merit (FOM) in compression with the previous works.
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[22] Z. Yan, P. I. Mak, R. P Martins, "Two stage operational amplifiers: Power and area efficient frequency compensation for driving a wide range of capacitive load", IEEE Circuits and Systems Magazine, vol 11, no. 1, pp. 26-42, 2011 (doi: 0.1109/mcas.2010.939783).
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[29] J. Luo, L. Wei, C. S. Lee, A. D. Franklin, X. Guan, E. Pop, D. A. Antoniadis, H. S. P. Wong, "Compact model for carbon nanotube field-effect transistors including nonidealities and calibrated with experimental data down to 9-nm gate length", IEEE Trans. Electron Devices, vol. 60, no. 6, pp.1834-1843, 2013 (doi: 10.1109/ted.2013.2258023).
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[32] B. Wen, Q. Zhang, X. Zhao, "A two-stage CMOS OTA with enhanced transconductance and DC-gain", Analog Integrated Circuits and Signal Processing, vol. 98, no. 2, pp. 257-264, 2019 (doi: 10.1007/s10470-018-1281-7).
[33] H. Veldandi, R. A. Shaik, "Low-voltage PVT-insensitive bulk-driven OTA with enhanced DC gain in 65-nm CMOS process", AEU-International Journal of Electronics and Communications, vol. 90, pp.88-96, 2018 (doi: 10.1016/j.aeue.2018.03.033).
_||_[1] B. Razavi, "Design of analog CMOS integrated circuits", Second Edition, New York, NY: McGraw-Hill, 2017.
[2] D. A. Johns, K. Martin, ''Analog integrated circuit design'', First Edition, New York, John Wiley & Sons, 2008.
[3] N. Dehabadi, R. Faghih Mirzaee, “Ternary DCVS half adder with built-in boosters”, Journal of Intelligent Procedures in Electrical Technology, vol. 11, no. 42, pp. 41-56, Summer 2020 (in Persian).
[4] S. Tabakhi, F. Razaghian, “Wide tuning range gm-c low-pass filter optimization with 10 MHz cut-off frequency for wireless applications”, Signal Processing and Renewable Energy, vol. 2, no. 3, pp. 15-20, Summer 2018.
[5] S. Rezaei Borjlu, H. Alibagheri, “Design and simulation of a 20-watt doherty power amplifier at a frequency of 2.14 GHz for wireless communication systems”, Journal of Intelligent Procedures in Electrical Technology, vol. 10, no. 37, pp. 23-30, Spring 2019 (in Persian).
[6] P. R. Gray, P. Hurst, R. G. Meyer, S. Lewis, "Analysis and design of analog integrated circuits", First Edition, New York, John Wiley & Sons, 2001.
[7] F. Sharifi, A. Panahi, M. H. Moaiyeri, H. Sharifi, K. Navi, "High performance CNFET-based ternary full adders", IETE Journal of Research, vol. 64 no.1, pp. 108–115. Jan 2018 (doi: 0.1080/03772063.2017.1338973).
[8] P. Keshavarzian, R. Sarifkhani, "A novel CNTFET-based ternary full adder", Circuits, Systems, and Signal Processing, vol. 33, no. 3, pp.665–679, 2014 (doi: 10.1007/s00034-013-9672-6).
[9] I. M. Salehabad, K. Navi, M. Hosseinzadeh, "Two novel inverter-based ternary full adder cells using CNFETs for energy-efficient applications", International Journal of Electronics, vol. 105, no. 10, pp.82–98, 2019 (doi: 10.1080/00207217.2019.1636306).
[10] M. H. Bagheri, M. Bagherizadeh,; M. Moradi, M. H. Moaiyeri, "Design of CNTFET-based current-mode multi-input m: 3 (4≤m≤7) Counters". IETE Journal of Research, pp.1-11, 2018 (doi: 10.1080/03772063.2018.1553640).
[11] S. Tabrizchi, A. Panahi, F. Sharifi, K. Navi, N. Bagherzadeh, "Method for designing ternary adder cells based on CNFETs", IET Circuits, Devices & Systems, vol. 11, no.5, pp. 465–470, 2017 (doi: 10.1049/iet-cds.2016.0443).
[12] A. T. Mahani, P. Keshavarzian, "A novel energy-efficient and high-speed full adder using CNTFET", Microelectronics Journal, vol. 61, no. 1, pp. 79–88, 2017 (doi: 10.1016/j.mejo.2017.01.009).
[13] M. Yasir, N. Alam, "Design of CNTFET-Based CCII Using gm/ID Technique for Low-Voltage and Low-Power Applications", Journal of Circuits, Systems and Computers, 29, no. 09, pp. 2050143, 2019 (doi: 10.1142/s0218126620501431).
[14] S. M. A. Zanjani, M. Dousti, M. Dolatshahi, "High-precision, resistor less gas pressure sensor and instrumentation amplifier in CNT technology", AEU-International Journal of Electronics and Communications, vol. 93, pp. 325-336, 2018 (doi: 10.1016/j.aeue.2018.06.018).
[15] S. M. A. Zanjani, M. Dousti, M. Dolatshahi, "Inverter-based, low-power and low-voltage, new mixed-mode Gm-C filter in subthreshold CNTFET technology". IET Circuits, Devices & Systems, vol. 12, no. 6, pp. 681-688, 2018 (doi: 10.1049/iet-cds.2018.5158).
[16] H. Mahmoodian, M. Dolatshahi, "An energy-efficient sample-and-hold circuit in CNTFET technology for high-speed applications", Analog Integrated Circuits and Signal Processing, pp. 1-13, vol. 103, March 2020 (doi: 10.1007/s10470-020-01607-y).
[17] P. A. Gowri sanNara, K. UdhayaNumarb, "A novel carbon nanotube field effect transistor based arithmetic computing circuit for low-power analog signal processing application", Procedia Technology, no.12, pp. 154-162, 2014 (doi: 10.1016/j.protcy.2013.12.469).
[18] M. Yasir, N. Alam, "Systematic design of CNTFET based OTA and Op amp using g m/I D technique". Analog Integrated Circuits and Signal Processing, vol. 102, issue 2, pp. 293-307, 2020 (doi: 10.1007/s10470-019-01492-0).
[19] M. Cen, S. Song, C. Cai, "A high performance CNFET-based operational transconductance amplifier and its applications", Analog Integrated Circuits and Signal Processing, vol. 91, issue 3, pp. 463-472, 2017 (doi: 10.1007/s10470-017-0951-1).
[20] J. Mahattanakul, J. Chutichatuporn, "Design procedure for two-stage CMOS op amp with flexible noise-ower balancing scheme", IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 52, no. 8, pp. 1508-1514, 2005 (doi: 10.1109/tcsi.2005.851395).
[21] B. Wen, Q. Zhang, X. Zhao, "A two-stage CMOS OTA with enhanced transconductance and DC-gain", Analog Integrated Circuits and Signal Processing, vol. 98, no. 2, pp. 257-264, 2019 (doi: 10.1007/s10470-018-1281-7).
[22] Z. Yan, P. I. Mak, R. P Martins, "Two stage operational amplifiers: Power and area efficient frequency compensation for driving a wide range of capacitive load", IEEE Circuits and Systems Magazine, vol 11, no. 1, pp. 26-42, 2011 (doi: 0.1109/mcas.2010.939783).
[23] M. Yavari, "Hybrid cascode compensation for two-stage CMOS opamps", IEICE Trans. on Electronics, vol. 88, no. 6, pp. 1161-1165, 2005 (doi: 0.1109/date.2006.244037).
[24] L. H.Ferreira, T. C. Pimenta, R. L. Moreno, "An ultra-low-voltage ultra-low-power CMOS Miller OTA with rail-to-rail input/output swing", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 54, no. 10, pp. 843-847, 2007 (doi: 10.1109/tcsii.2007.902216).
[25] D. Marano, A. D. Grasso, G. Palumbo, S. Pennisi, "Optimized active single-miller capacitor compensation with inner half-feedforward stage for very high-load three-stage OTAs", IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 63, no. 9, pp.1349-1359, 2016 (doi: 10.1109/tcsi.2016.2573920).
[26] H. Veldandi, R. A. Shaik, "An ultra-low-voltage bulk-driven analog voltage buffer with rail-to-rail input/output range", Circuits, Systems, and Signal Processing, vol. 36, no. 12, pp. 4886-4907, 2017 (doi: 10.1007/s00034-017-0663-x).
[27] J. Mahattanakul, "Design procedure for two-stage CMOS operational amplifiers employing current buffer", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 52, no. 11, pp.766-770, 2005 (doi: 10.1109/tcsii.2005.852530).
[28] S. K. Rajput, B. K. Hemant, "Two-stage high gain low power opamp with current buffer compensation", Proceeding of the IEEE/GHTCE, pp. 121-124, Shenzhen, China, Nov. 2013 (doi: 0.1109/ghtce.2013.6767255).
[29] J. Luo, L. Wei, C. S. Lee, A. D. Franklin, X. Guan, E. Pop, D. A. Antoniadis, H. S. P. Wong, "Compact model for carbon nanotube field-effect transistors including nonidealities and calibrated with experimental data down to 9-nm gate length", IEEE Trans. Electron Devices, vol. 60, no. 6, pp.1834-1843, 2013 (doi: 10.1109/ted.2013.2258023).
[30] L. Zuo, S. K. Islam, "Low-voltage bulk-driven operational amplifier with improved transconductance", IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 60, no. 8, pp. 2084-2091, 2013 (doi: 10.1109/tcsi.2013.2239161).
[31] J. M. Carrillo, G. Torelli, M. A. Domínguez, J. F. Duque‐Carrillo, "On the input common‐mode voltage range of CMOS bulk‐driven input stages", International Journal of Circuit Theory and Applications, vol. 39, no 6, pp. 649-664, 2011 (doi: 10.1109/ecctd.2009.5274938).
[32] B. Wen, Q. Zhang, X. Zhao, "A two-stage CMOS OTA with enhanced transconductance and DC-gain", Analog Integrated Circuits and Signal Processing, vol. 98, no. 2, pp. 257-264, 2019 (doi: 10.1007/s10470-018-1281-7).
[33] H. Veldandi, R. A. Shaik, "Low-voltage PVT-insensitive bulk-driven OTA with enhanced DC gain in 65-nm CMOS process", AEU-International Journal of Electronics and Communications, vol. 90, pp.88-96, 2018 (doi: 10.1016/j.aeue.2018.03.033).
