Multipath cascaded single stage distributed power detector; analysis and design
محورهای موضوعی : Electrical EngineeringNader Javadifar 1 , Yaghoob Mohammadmoradi 2 , Atila skandarnezhad 3
1 - Department of Electrical Engineering , Aliabad Katoul Branch, Islamic Azad University, Aliabad Katoul ,Iran
2 - Department of Physics, Aliabad Katoul Branch, Islamic Azad University, Aliabad Katoul, Iran
3 - Department of Electrical Engineering, Aliabad Katoul Branch, Islamic Azad University, Aliabad Katoul, Iran
کلید واژه: distributed circuit, logarithmic amplifier, microwave, power detector, transmission line,
چکیده مقاله :
In this paper, a novel technique to improve the input dynamic range and bandwidth of the microwave power detectors (PDs) simultaneously is presented, which utilizes the piecewise linear approximation in conjunction with the distributed structure to achieve the goals. RF to DC conversion is proved for the proposed PD core, including only a MOS transistor that is capable to convert a part of its RF input signal to a DC value, proportional to the RF input power. This is an efficient method that requires less number of active devices and therefore saves more power consumption and active chip area, rather than the previous conventional methods. The analysis of circuit based on the transmission line theory is discussed and the transfer function is extracted mathematically for the proposed model. Moreover, a transistor level design is performed using a 0.15um pHEMT GaAs technology for 24GHz applications. The post layout simulation results are presented.
In this paper, a novel technique to improve the input dynamic range and bandwidth of the microwave power detectors (PDs) simultaneously is presented, which utilizes the piecewise linear approximation in conjunction with the distributed structure to achieve the goals. RF to DC conversion is proved for the proposed PD core, including only a MOS transistor that is capable to convert a part of its RF input signal to a DC value, proportional to the RF input power. This is an efficient method that requires less number of active devices and therefore saves more power consumption and active chip area, rather than the previous conventional methods. The analysis of circuit based on the transmission line theory is discussed and the transfer function is extracted mathematically for the proposed model. Moreover, a transistor level design is performed using a 0.15um pHEMT GaAs technology for 24GHz applications. The post layout simulation results are presented.
[1] Huggins, R. W. "Analytical fit of the transfer function of a logarithmic electrometer and correction for ambient temperature variations," Review of Scientific Instruments, 1973, Vol. 44, no.3, pp. 297–300.
[2] Meyer, R.: "Low power monolithic RF peak detector analysis," IEEE J. Solid-State Circuits, 1995, Vol. 30, no.1, pp. 65–67.
[3] Wilson, B., & Al-Gahtani, M. "Improved logarithmic converter based on a transconductance feedback amplifier," In the 2001 IEEE international symposium on circuits and systems ISCAS, Vol. 1, pp. 651–654.
[4] Rami, S., Tuni, W., and Eisenstadt, W.R. ‘Millimeter wave MOSFET amplitude detector’, IEEE Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2010, pp. 84–87
[5] Huang, C., & Chakrabartty, S. "Current-input current-output CMOS logarithmic amplifier based on translinear Ohm’s law," Electronics Letters, 2011, Vol. 47, no.7, pp. 433–434.
[6] K. A. Townsend and J. W. Haslett, “A wideband power detection system optimized for the UWB spectrum”, IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 371–381, Feb. 2009.
[7] Barber, W. L., & Brown, E. R., "A true logarithmic amplifier for radar IF applications," IEEE Journal of Solid-State Circuits, 1980, Vol. 15, no.3, pp. 291–295.
[8] Wu, J., Hsu, K., Lai, W., To, C., Chen, S., Tang, C., and Juang, Y.: "A linear-in-dB radio-frequency power detector," IEEE Microwave Symposium Digest (MTT), 2011, pp. 1-4.
[9] K. Kiela, M. Jurgo, and R. Navickas, “Design of a linear-in-dB power detector in 65nm CMOS technology”, ELEKTRONIKA IR ELEKTROTECHNIKA, 2013, Vol. 19, no. 10, pp. 91-94.
[10] Haynes, M.: "Wideband Monolithic SDLA Design Using InP DHBT Technology," IET Seminar on RF and Microwave IC Design, 2008, pp. 1-6.
[11] Kenneth A. Townsend, James W. Haslett, "A Wideband Power Detection System Optimized for the UWB Spectrum," IEEE Journal of Solid-State Circuits, Vol. 44, No. 2, February, 2009.
[12] R. Michels, N. Scheinberg, J. Gluck, "An L-Band Temperature Compensated Ultra Low Power Successive Detection Logarithmic Amplifier," IEEE MTT-S International Microwave Symposium Digest, pp. 541-4, 1989.
[13] G. M. Gorman, A. K. Oki, E. M. Mrozek, J. B. Camou, D. K. Umemoto, and M. E. Kim, "A GaAs HBT Monolithic Logarithmic IF (0.5 TO 1.5 GHz) Amplifier with 60 dB Dynamic Range and 400 mW Power Consumption," IEEE MTT-S Digest, vol.2, pp. 537-540, 1989.
[14] R. S. Hughes, Logarithmic Amplification with Application to Radar and EW. Dedham, Artech House, 1986.
[15] P.-C. Huang, Y.-H. Chen, and C.-K. Wang, "A 2-V 10.7-MHz CMOS limiting amplifier/RSSI," IEEE J. of Solid-State Circuits, vol. 35, no. 10, pp. 1474–1480, Oct. 2000.
[16] A. Hajimiri, "Distributed Integrated Circuits: An Alternative Approach to High-Frequency Design," IEEE Communication Magazine, 2002, Vol. 40, no. 2, pp. 168-173.
[17] Kambiz Moez and Mohamed Elmasry, "A Low-Noise CMOS Distributed Amplifier for Ultra- Wideband Applications," IEEE Transactions on Circuits and Systems II, Vol. 55, no. 2, pp 126-130, Feb. 2008.
[18] A. Ghadiri and K. Moez, "Compact Transformer-Based Distributed Amplifier for UWB Systems," IEEE Transactions on Circuits and Systems - II: Express Briefs, vol. 58, no. 5, pp. 259-263, May 2011.
[19] Wai-Kai Chen, "Theory and design of distributed amplifiers," International Journal of Electronics, vol.26, no. 5, pp. 405-421, 1969.
[20] Kenji Kumabe and Hiroshi Kanbe, "GaAs travelling-wave amplifier," International Journal of Electronics, vol. 58, no. 4, pp. 587-611, 1985.
[21] H. Wu and A. Hajimiri, "Silicon-Based Distributed Voltage Controlled Oscillator," IEEE J. Solid-State Circuits, Mar. 2001.
[22] Aoki, I.; Kee, S.D.; Rutledge, D.B.; Hajimiri, A., "Fully integrated CMOS power amplifier design using the distributed active-transformer architecture," J. Solid-State Circuits, vol.37, no.3, pp.371-383, Mar. 2002.
[23] Valdes-Garcia, A., Venkatasubramanian, R., Srinivasan, R., Silva-Martinez, J., & Sinencio E. S. "A CMOS RF rms detector for built in testing of wireless transceivers," 23rd IEEE VLSI Test Symposium, doi:10.1109/VTS.2005.8.
[24] Yin, Q., Eisenstadt, W. R., Fox, R. M., & Zhang, T. (2005). "A translinear rms detector for embedded test of RF ICs," IEEE Trans. On Instrumentation and Measurement, doi:10.1109/TIM.2005.855105.
[25] H. Wu and A. Hajimiri, "Silicon-Based Distributed Voltage Controlled Oscillator," IEEE J. Solid-State Circuits, Mar. 2001.
[26] Liang, J. Y. and C. S. Aitchison, "Gain Performance of Cascade of Single Stage Distributed Amplifiers," Electronics Letters, Vol. 31, No. 15, July 1995, pp.1260-1261.
Journal of Applied Dynamic Systems and Control, Vol.7, No.1, 2024: 55-64 | 55 |
Multipath Cascaded Single Stage Distributed Power Detector; Analysis and Design
Nader Javadifar1*, Yaghoob Mohammadmoradi2, Atila skandarnezhad3
1* Corresponding Author: Department of Electrical Engineering , Aliabad Katoul Branch,Islamic Azad University, Aliabad Katoul, Iran.
Email: javadifar@aliabadiau.ac.ir
2 Department of Physics , Aliabad Katoul Branch,Islamic Azad University, Aliabad Katoul, Iran.Email: mohammadmoradi@aliabadiau.ac.ir
3 Department of Electrical Engineering , Aliabad Katoul Branch,Islamic Azad University, Aliabad Katoul, Iran.
Email: eskandarnejad@aliabadiau.ac.ir
Received: 2024.01.13 ; Accepted:2024.04.13
Abstract – In this paper, a novel technique to improve the input dynamic range and bandwidth of the microwave power detectors (PDs) simultaneously is presented, which utilizes the piecewise linear approximation in conjunction with the distributed structure to achieve the goals. This is an efficient method that requires less number of active devices and therefore saves more power consumption and active chip area, rather than the previous conventional methods. The analysis of circuit based on the transmission line theory is discussed and the transfer function is extracted mathematically for the proposed model. Moreover, a transistor level design is performed using a 
PHEMT GaAs technology for 
applications. The post layout simulation results are presented.
Keywords: Distributed circuit; Logarithmic amplifier; Microwave; Power detector; Transmission line.
1. Introduction
Many of applications such as wireless communication systems and test & measurement equipment need to detect radio frequency (RF) signals at very weak levels. Signal level can be detected by generating an output proportional to the power of input signal.
On the other hand, the power level of RF signals in many cases varies in the wide range of multi octave in decibel (dB). For that reason, the linear amplifiers are inefficient to detect such signals, because they have a limited dynamic range.
An alternative approach has been used is the logarithmic amplifiers (commonly known as log-amps). The log-amps are divided into the two main categories: The first, those that utilize the inherent exponential characteristic of the semiconductor devices such as p-n junction diodes [1], bipolar transistors [2], [3] and MOSFET transistors in weak inversion region [4-6]. However, they don't have a wide dynamic range usually. Furthermore, the operation of these devices is restricted at higher frequencies, because of the modification of their fundamental characteristic equation by parasitic elements [7]. To extend the total input dynamic range, the second type of log-amps employs more complex configuration with multiple parallel paths. The successive detection logarithmic amplifier (SDLA) is the most famous configuration, which uses this approach to realize the approximated logarithmic function (Fig. 1) [8-13].
Fig.1. General block diagram of SDLA
The SDLA is conventionally made up of a number of limiting-amplifier stages in a cascaded manner. Each amplifier drives a detector cell (or rectifier cell) to convert its RF input signal to a DC voltage proportional to the amplitude of the RF input. Sum of the detector cells output forms a desired logarithmic transfer function by using the piecewise linear approximation method [14]. The more number of stages in this circuit, results in a wider dynamic range. However, this decreases the total bandwidth of circuit as below [15]:
(1)
Where 
indicates the total bandwidth of the cascaded circuit with 
gain stages and 
is the bandwidth of a single gain stage. Therefore, a very strict trade-off between the total dynamic range and frequency of operation exists in this topology, where improving one proportionally degrades the other.
In this paper, a microwave PD based on the SDLA structure in combination with distributed circuit theory is proposed to overcome this challenge. Section II, describes the principle of PD design based on the distributed circuit concept. The analysis and design of proposed distributed PD is presented in section III. The post layout simulation results are shown in section IV, and finally a conclusion is given in section V.
2. Distributed PD concept and structure
The term 'distributed' has been used quite the opposite of the 'lumped' notion in many of literature. However, for the purposes of this paper, a distributed system is defined to be a system with multiple parallel signal paths and devices, cooperating in harmony to achieve a desired task [16]. On the basis of this definition, the distributed circuit configuration is in contrast to the conventional serial cascaded systems, which have a single signal path. In addition, the physical size of the circuit compared with the signal wavelength has no importance in this view.
As mentioned in the preceding section, the total bandwidth of an analog cascaded circuit block decreases by increasing the number of cascaded stages. This stems from this fact that the more number of stages (or sections), imposes additional poles to the circuit. In distributed systems, however, the core of a given circuit is placed in the multiple parallel paths between the two artificial transmission lines, so that the parasitic capacitances may be absorbed into the line's LC sections. The examples of such circuits has been presented previously are distributed amplifier (DA) [17-20], distributed voltage controlled oscillator (DVCO) [21] and distributed active transformer (DAT) power amplifier [22].
Generalize this idea to logarithmic detector topologies such as SDLA, necessitates exploitation of the two transmission lines (including on-chip passive lumped inductors) that the core of PD circuit is embedded between them and through which the RF input signal can travel without deterioration of the bandwidth. The parasitic capacitances will be merged with the lumped inductors in this condition and the artificial transmission lines are constructed. This technique allows the core of PD is repeated in a cascaded structure to extend the total dynamic range without sacrificing the bandwidth.
Fig. 2 shows the simplified schematic of the proposed PD core, which is suggested based on the described idea. This comprises a single stage DA as an amplifier stage followed by a simple common gate MOS as a detector cell.
The parasitic capacitances in connection with the amplifier stage are absorbed into the two artificial transmission lines, which we called them input line and inter-stage line, respectively. The detector cell parasitic capacitances at its input node are also absorbed into the inter-stage line. Because of the desired signal at the PD output is the DC portion, there is no concern associated with the parasitic capacitances at the output tips of the detector cell.
Fig. 2. Simplified schematic of proposed PD core
The power detection investigation by using the above PD core will be described in the next section. Moreover, we will exploit the proposed PD core in a SDLA structure to extend the total dynamic range. Extraction of the logarithmic function for the SDLA will be presented subsequently.
3. Circuit analysis and design
3.1. RF to DC conversion for the proposed PD core
The power detection process is often performed in three steps: V/I (voltage to current) conversion, RF to DC conversion and finally I/V conversion [4], [23-24]. A voltage may be converted to current easily by using a MOS transistor through its transconductance. Moreover, the RF to DC conversion can be realized by using a single MOS transistor in one of the common-source, common-drain or common-gate forms, like those we have proposed as a detector cell in Fig. 2. We will prove this claim in the continuation.
As seen from Fig. 2, the amplifier stage in the proposed PD core is a single stage DA, comprises an active device (M1) and the two LC ladders at its input and output as a transmission line. The detector cell is a simple common gate transistor M2, which produces a DC voltage proportional to the power of amplified RF signal at the drain of M1. The parasitic capacitances of M1 and M2 in conjunction with the lumped inductors of the input and inter-stage lines make the two artificial transmission lines. Contrary to conventional DA structure, the idle drain line termination (marked with dotted line in this figure) has been eliminated in this configuration. Therefore, the voltage swing across the output drain of M1 is increased, which consequently enhances the amplifier's gain.
In general, the transfer characteristic curve of a linear amplifier may be shown as Fig. 3. As seen, a linear amplifier has the two operation modes. If the input signal amplitude is less than a threshold value of 
, then it works in amplifying (or linear) mode and if the amplitude is larger than this value, the amplifier is forced to operate in limiting mode.
|
Fig. 3. General characteristic curve of a linear amplifier
By assumption that the single stage DA in Fig. 2 operates in linear mode, its output is a sine wave proportional to the RF input signal. In this condition, the detector transistor M2 meets a sine wave at its input.
The instantaneous current at the output of detector cell, now is given by:
(2)
where the 
and 
indicate the DC and AC portion of the gate to source voltage of M2, respectively and 
is the threshold voltage. From above, the instantaneous current of detector cell can be divided into the two individual parts, we name them 
and 
. The first part, 
, is a DC portion due to the biasing voltage and just affects the DC offset of the output current. The second part, 
, originates from the RF signal at the input of M2.
By considering the RF input signal of the detector cell transistor M2 as 
and from the simplified schematic of Fig. 2, we have:
(3)
Substituting (3) into the second part of equation (2), gives:
(4)
By considering the RF received signal at the gate of M1 equal to
, magnitude of amplified signal at its output is given by:
(5)
The artificial transmission lines have been supposed lossless in above equation. From (4) and (5), we have:
(6)
A low-pass RC filter at the output eliminates the AC terms and so a constant DC current remains as:
(7)
This proves a MOS transistor is capable to convert a part of its RF input signal to a DC value, proportional to the RF input power. If the amplifier stage operates in limiting mode, its output is a constant saturated voltage of 
and therefore there is no RF signal at the input of detector cell (i.e.,
). Accordingly, the detector cell adds just a constant DC current to output, independent of an RF input signal amplitude.
3.2.Multipath cascaded single stage distributed power detector
The PD core proposed in previous section was designed based on the distributed circuit theory, especially to operate at microwave frequencies using minimum active devices. Nevertheless, it has a limited dynamic range and has not sufficient sensitivity to detect very week RF signals. Accordingly, a proper enhancement must be done for this structure to increase the dynamic range using the logarithmic topologies.
At first glance, it maybe seems that achieving a logarithmic transfer function is possible by developing the proposed PD core in a parallel summation schematic of Fig. 4(a). Indeed, this structure is the well-known topology of DA that each section drives a detector cell at its output. The main drawback concerned with this structure is the additive gain nature of the DA. Assuming that the transmission lines are lossless, the voltage gain at the last section of the DA drain line can be estimated by [25]:
(8)
As seen, no logarithmic function can be derived from this equation.
As an alternative, we can use the proposed PD core in a multipath cascaded single stage distributed power detector (CSSDPD) configuration of Fig. 4(b), which is inspired from the SDLA configuration. The complete circuit schematic along with the biasing network has been indicated in this figure.
(a)
(b)
Fig. 4. a) Extension of the proposed PD core with additive gain nature; b) A complete schematic of the multipath CSSDPD with multiplicative gain nature.
Cascade of single stage distributed amplifier stages takes advantage of multiplicative gain feature [26]. This arises from the fact that the RF input signal is multiplied by the gain of each amplifier stage and so emerges multiplicatively at the input of subsequent stages. Summing the detected signal of each core through the multiple parallel paths successively approximates the desired logarithmic transfer function at the output node [14].
There are two artificial transmission lines in this configuration. One of them is the input line of the first stage PD core, we called it 'input line'. Another is called 'inter-stage line', which includes all of the other transmission lines. Only the input line must be terminated to 
. There is no necessity for the inter-stage transmission lines to be matched to . This gives the more degree of freedom to design this circuit and allows the inter-stage lines to have a larger characteristic impedance, which means attaining a given gain requirement by using the less number of sections compared with the conventional DA structure. Additionally, this consumes lower power and occupies lower chip area. Unlike the usual structure of DA, the phase velocity equalization is not mandatory in this circuit, also.
Another problem related with the DA is the lossy nature of transmission lines, which results from the low quality of on-chip inductors. Accordingly, the losses in the long artificial transmission lines may be greater than the amount of signal amplification. This provides extra restrictions on this circuit, from the viewpoint of maximum number of sections. It is in contrary to achieve a large dynamic range. Cascade of single stage DA (in Fig. 4(b)) can solve this problem, also. Because the transmission lines are not continuous in this topology and the line of each section is separated from the others. However, an additional capacitor (
) is probably required in each inter-stage line of CSSDPD, to equalize the LC sections capacitance.
The bandwidth of proposed CSSDPD is restricted here by minimum cut-off frequency of the two transmission lines. Supposing all sections are similar, the cut-off frequency of two transmission lines and their characteristic impedance can be expressed as:
(9)
A mathematical analysis to derive a logarithmic transfer function for this circuit is provided in next section.
3.3. Transfer function extraction
From the Fig. 4(b), by considering the RF input signal as 
and the voltage gain of amplifier stages in linear mode as 
, the voltage at drain tips of amplification transistors are given as:
(10)
Where 
the transconductance of the amplifier is stages and 
is the voltage at the gate of 
amplification transistor. Multiplicative gain can be obviously observed from these equations.
The gate voltage of each amplifier may be expressed as:
(11)
On the other hand, the DC converted current at the output of 
path may be rewritten by generalizing the equation (7) as following:
(12)
In above, 
is the peak of voltage magnitude at the gate of amplifying transistor in
section.
For a multipath CSSDPD with stages, when all amplifier stages are in linear mode, the converted DC current of each path can be written as below:
(13)
In limiting mode also, the amplifier stages output has a saturated value of and the output of paths in this case considered as a constant value of 
.
By boosting the RF input signal in the cascaded structure, some of the amplifier stages may be in linear mode and some others in limiting mode. As a result, the converted DC currents summation of parallel paths at output node may have 
situations:
(14)
In above, 
indicates the converted DC output current at 
situation, when 
stages operate in linear mode and (
) ones in limiting mode.
From (14), given the RF input voltage is at its lower boundary at situation, i.e. 
, we have:
(15)
Replacing (13) in (14) for thesituation gives us:
(16)
The above equation by assumption that the gain of linear mode (
) is sufficiently greater than 1, can be approximated as:
(17)
Substituting (15) in above and using straightforward calculations, the DC output current at situation is given by:
(18)
The derived equation shows a logarithmic relationship between the output current of CSSDPD and the amplitude of RF input signal explicitly. The term 
is a constant value which indicates the slope of logarithmic function. The term 
is reversely proportional to the number of sections () and will decrease by increasing . This determines the beginning point of the logarithmic function, so that when the RF input signal amplitude (
) reaches this value, 
will be zero. Accordingly, the more number of sections cause to decrease the minimum detectable input signal and increases the sensitivity.
4. Simulation results, layout and comparison
Over the microwave frequencies, the atmospheric loss meets a peak near the centre of band
, which mainly occurs due to the absorption by water vapor molecules. Consequently, detecting the RF signals at this band encounters a challenge especially for those applications trying to cover distances of more than a few kilometers. This necessitates the design of power detectors with very high sensitivity for this band.
Here, the simulation results of a logarithmic power detector for band based on the twelve stage CSSDPD circuit by using the PHEMT GaAs technology is presented.
4.1. Simulation results of PD core
Fig. 5(a) depicts the DC portion of output voltage for the proposed PD core versus the RF input amplitude sweep from 
to 
. The curve shown in this figure, belongs to an even function of equation (7) and confirms that the output characteristic of the proposed PD core is similar to those which can be achieved by a full-wave rectifier. Accordingly, the proposed PD core can do the desired task with just one active device, which is much lower than those are required by a full-wave rectifier in conventional SDLA configuration [8-10].
Fig. 5(b) indicates the transient response of output voltage versus the RF input amplitude variations from 
to 
. This shows the DC portion of output voltage increases by increasing the RF input amplitude and proves the RF input signal is converted to a DC voltage proportionally by the proposed PD core. The ripples are seen in this figure can be alleviated by applying a larger load capacitor 
in the output RC filter (shown in Fig. 2).
Fig.5(a). The DC component of output voltage as a function of input amplitude
Fig. 5(b). Transient response of the proposed PD core for 
4.2. Simulation results for the twelve stage multipath CSSDPD
Fig. 6 depicts the DC output voltage of the twelve stage CSSDPD versus the amplitude of RF input. The logarithmic behavior is obvious in this figure.
Moreover, the transfer characteristic of proposed power detector and its detection error is shown in Fig.7. Indeed, this figure is the same as Fig. 6, except that the horizontal axis is in logarithmic form. As seen, the total dynamic range is 
from 
to 
and the maximum detection error over the dynamic range is 
. Minimum detectable power is 
, which shows an ultra-high sensitivity.
Fig. 8 shows the total power gain
and the input return loss 
in dB. As shown, the power gain is very flat 
over the frequency band. Moreover, 
is less than 
over the operating frequency range, which boasts ease of input matching for the cascaded single stage DA topology.
Fig. 6. DC output voltage of CSSDPD versus the RF input amplitude
f=24.0 GHz f=24.1 GHz f=24.2 GHz f=24.3 GHz
|
Fig.7. Transfer characteristic of the twelve stage CSSDPD and its error
Fig.8. S-parameters of twelve stage CSSDPD
The layout of the designed power detector is shown in Fig.9. The total chip area including twelve stages, supplies nets and pads is
. This is 
for each PD core. The total power consumption is 
from 
power supplies.
Fig. 9. Layout of the designed multipath CSSDPD
Table 1 summarizes the proposed power detector characteristics and compares this work with others.
Table1. Comparison of logarithmic power detectors
Ref. no. | Freq. (GHz) | Dynamic range (dB) | Logging error (dB) | Power cons. (mW) | Supply voltage (V) | Topology &Technology |
[8] | DC to 8 | 40 60 |
| 70 150 | 2.8 | (SDLA) 180nm CMOS (measured) |
[9] | 1 | 65 74 |
| 24 | 1.2 | (SDLA) 65nm CMOS (simulated) |
[10] | 2 to 18 | 33 |
| 690 | -5 | (SDLA) InP DHBT (measured) |
[12] | 0.5 to 1.2 | 60 |
| 700 | NA | (SDLA) GaAs (measured) |
[13] | 0.5 to 1.5 | 60 |
| 400 |
| (SDLA) GaAs HBT (measured) |
This work | 24 to 24.3 | 95 110 |
| 194 |
| (SDLA) 0.15 (simulated) |
5. Conclusion
In this study, the theory of a linear-in-dB microwave power detector with novel structure was analyzed and mathematically discussed. The PD core configuration exploited here is ultra wideband and requires the minimum number of transistors. A significant progress has been made in extending the dynamic range at frequencies of more than 
, while keeping the power consumption as low as possible. The total dynamic range of with the minimum detectable power of 
has been achieved. The detection error over the total dynamic range is less than
. It is also less than 
from to
. The total power consumption of designed power detector is.
REFERENCES
[1] Huggins, R. W. "Analytical fit of the transfer function of a logarithmic electrometer and correction for ambient temperature variations," Review of Scientific Instruments, 1973, Vol. 44, no.3, pp. 297–300.
[2] Meyer, R.: "Low‑power monolithic RF peak detector analysis," IEEE J. Solid-State Circuits, 1995, Vol. 30, no.1, pp. 65–67.
[3] Wilson, B., & Al-Gahtani, M. "Improved logarithmic converter based on a transconductance feedback amplifier," In the 2001 IEEE international symposium on circuits and systems ISCAS, Vol. 1, pp. 651–654.
[4] Rami, S., Tuni, W., and Eisenstadt, W.R. ‘Millimeter wave MOSFET amplitude detector’, IEEE Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2010, pp. 84–87
[5] Huang, C., & Chakrabartty, S. "Current-input current-output CMOS logarithmic amplifier based on translinear Ohm’s law," Electronics Letters, 2011, Vol. 47, no.7, pp. 433–434.
[6] K. A. Townsend and J. W. Haslett, “A wideband power detection system optimized for the UWB spectrum”, IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 371–381, Feb. 2009.
[7] Barber, W. L., & Brown, E. R., "A true logarithmic amplifier for radar IF applications," IEEE Journal of Solid-State Circuits, 1980, Vol. 15, no.3, pp. 291–295.
[8] Wu, J., Hsu, K., Lai, W., To, C., Chen, S., Tang, C., and Juang, Y.: "A linear-in-dB radio-frequency power detector," IEEE Microwave Symposium Digest (MTT), 2011, pp. 1-4.
[9] K. Kiela, M. Jurgo, and R. Navickas, “Design of a linear-in-dB power detector in 65nm CMOS technology”, ELEKTRONIKA IR ELEKTROTECHNIKA, 2013, Vol. 19, no. 10, pp. 91-94.
[10] Haynes, M.: "Wideband Monolithic SDLA Design Using InP DHBT Technology," IET Seminar on RF and Microwave IC Design, 2008, pp. 1-6.
[11] Kenneth A. Townsend, James W. Haslett, "A Wideband Power Detection System Optimized for the UWB Spectrum," IEEE Journal of Solid-State Circuits, Vol. 44, No. 2, February, 2009.
[12] R. Michels, N. Scheinberg, J. Gluck, "An L-Band Temperature Compensated Ultra Low Power Successive Detection Logarithmic Amplifier," IEEE MTT-S International Microwave Symposium Digest, pp. 541-4, 1989.
[13] G. M. Gorman, A. K. Oki, E. M. Mrozek, J. B. Camou, D. K. Umemoto, and M. E. Kim, "A GaAs HBT Monolithic Logarithmic IF (0.5 TO 1.5 GHz) Amplifier with 60 dB Dynamic Range and 400 mW Power Consumption," IEEE MTT-S Digest, vol.2, pp. 537-540, 1989.
[14] R. S. Hughes, Logarithmic Amplification with Application to Radar and EW. Dedham, Artech House, 1986.
[15] P.-C. Huang, Y.-H. Chen, and C.-K. Wang, "A 2-V 10.7-MHz CMOS limiting amplifier/RSSI," IEEE J. of Solid-State Circuits, vol. 35, no. 10, pp. 1474–1480, Oct. 2000.
[16] A. Hajimiri, "Distributed Integrated Circuits: An Alternative Approach to High-Frequency Design," IEEE Communication Magazine, 2002, Vol. 40, no. 2, pp. 168-173.
[17] Kambiz Moez and Mohamed Elmasry, "A Low-Noise CMOS Distributed Amplifier for Ultra- Wideband Applications," IEEE Transactions on Circuits and Systems II, Vol. 55, no. 2, pp 126-130, Feb. 2008.
[18] A. Ghadiri and K. Moez, "Compact Transformer-Based Distributed Amplifier for UWB Systems," IEEE Transactions on Circuits and Systems - II: Express Briefs, vol. 58, no. 5, pp. 259-263, May 2011.
[19] Wai-Kai Chen, "Theory and design of distributed amplifiers," International Journal of Electronics, vol.26, no. 5, pp. 405-421, 1969.
[20] Kenji Kumabe and Hiroshi Kanbe, "GaAs travelling-wave amplifier," International Journal of Electronics, vol. 58, no. 4, pp. 587-611, 1985.
[21] H. Wu and A. Hajimiri, "Silicon-Based Distributed Voltage Controlled Oscillator," IEEE J. Solid-State Circuits, Mar. 2001.
[22] Aoki, I.; Kee, S.D.; Rutledge, D.B.; Hajimiri, A., "Fully integrated CMOS power amplifier design using the distributed active-transformer architecture," J. Solid-State Circuits, vol.37, no.3, pp.371-383, Mar. 2002.
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