ارزیابی اثرحرارت،اغتشاش و نویز در تمام جمع کننده های مبتنی بر روشGDI
محورهای موضوعی : مهندسی الکترونیک
هاشم عرفاوی
1
(
دانشجوی کارشناسی ارشد، گروه مهندسی برق، واحد بوشهر، دانشگاه آزاد اسلامی، بوشهر، ایران
)
سید محمد علی ریاضی
2
(
گروه مهندسی برق، واحد بوشهر، دانشگاه آزاد اسلامی، بوشهر، ایران
)
روزبه حمزه ئیان
3
(
گروه مهندسی برق، واحد بوشهر، دانشگاه آزاد اسلامی، بوشهر، ایران
)
کلید واژه: بهره نویز واحد (UNG), روش GDI, تمام جمع کننده, منحنی مصونیت در برابر نویز (NIC), حاصلضرب توان-تاخیر(PDP),
چکیده مقاله :
در این مقاله، توجه خود را به تمام جمع‌کننده‌های مبتنی بر روش GDI محدود می‌کنیم، مدارهایی که معمولاً در مدارهای پرسرعت استفاده می‌شوند و بیشتر در معرض نویز هستند. تاکنون بررسی جامعی در مورد مصونیت در برابر نویز و تغییر دمای محیط تمام جمع‌کننده‌های مبتنی بر روش GDI ارائه نشده و اکثر مقالات طرح پیشنهادی خود را با سایر تمام جمع‌کننده‌ها مقایسه کرده‌اند که عمدتاً مبتنی بر روش GDI نیستند. این سلول‌های تمام جمع کننده با شبیه‌سازی‌های مختلفی از قبیل تغییر ولتاژ تغذیه، تغییر بار خازنی، تغییر دمای محیط و تغییرات ناشی از فرآیند، ولتاژ تغذیه و دما (PVT) در فناوری 45 نانومتر CMOS مورد ارزیابی قرار گرفتند. منحنی مصونیت در برابر نویز (NIC) برای سلول‌های تمام جمع کننده استخراج شد تا سلول‌های تمام جمع کننده با عملکرد بهتر مشخص شوند. بهره نویز واحد (UNG) نیز برای ارزیابی نویز بررسی شد. در نهایت مقایسه‌ای جامع از لحاظ تأخیر انتشار، توان مصرفی، حاصلضرب توان-تأخیر (PDP)، سوئینگ، حساسیت در برابر تغییرات فرآیند و نویز برای تمام جمع کننده‌های مبتنی بر روش GDI انجام شد. نتایج به‌دست‌آمده می‌تواند در تصمیم‌گیری طراحان مدار مجتمع برای انتخاب ساختار مناسب تمام جمع کننده مبتنی بر روش GDI مفید واقع شود.
In this paper, we limit our attention to full adders based on the GDI method, circuits that are commonly used in high-speed circuits and are more prone to noise. So far, a comprehensive review on noise immunity and ambient temperature change of full adders based on the GDI method has not been presented, and most of the studies have compared their proposed design with other full adders, which are mainly not based on the GDI method. These full adder cells were evaluated by various simulations such as supply voltage change, capacitive load change, ambient temperature change and process-voltage-temperature (PVT) changes in 45 nm CMOS technology. A noise immunity curve (NIC) was derived for full adder cells to identify better-performing full adder cells. The unity noise gain (UNG) was also investigated to evaluate the noise. Finally, a comprehensive comparison was made in terms of propagation delay, power consumption, power-delay product (PDP), voltage swing, sensitivity to process changes and noise for full adders based on the GDI method. The obtained results can be useful in the decisions of integrated circuit designers to choose the appropriate structure of the full adder based on the GDI method
[1] M. Sayyaf, A. Ghasemi, R. Hamzehyan, “Design of Low Power Single-Bit Full-Adder Cell Based on Pass-Transistor Logic,” Journal of Southern Communication Engineering, Articles in Press, Accepted Manuscript, Available Online from 14 July 2022, doi: 10.30495/jce.2022.692834 (in Persian).
[2] T. Rashedzadeh, S. M. A. Riyazi, N. Cheraghi Shirazi, “Analysis of the effect of changes of FINs Architectural on FINFET Drain current and on Average Power Dissipation and Propagation Delay in the Hybrid-CMOS full adder,” Journal of Southern Communication Engineering, vol. 10, no. 40, pp. 25-36, July 2021, (in Persian).
[3] A. Baghi Rahin and V. Baghi Rahin, “Ultra low voltage and low power 4-2 compressor using FinFET transistors,” Journal of Intelligent Procedures in Electrical Technology (JIPET), vol. 9, no. 33, pp. 25-36, May 2018, dor: 20.1001.1.23223871.1397.9.33.3.2.
[4] K. L. Shepard, “Design methodologies for noise in digital integrated circuits,” Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175), 1998, pp. 94-99, doi: 10.1145/277044.277062.
[5] N. Eshraghian, and K. Weste, Principles of CMOS VLSI Design. A System Perspective. Reading, MA: Addison-Wesley., 1993
[6] SIA National Technology Roadmap for Semiconductors. SE-MATECH, Inc., 1997.
[7] A. Baghi Rahin and V. Baghi Rahin, “A New 2-input CNTFET-Based XOR Cell With Ultra-Low Leakage Power For Low-Voltage and Low-Power Full Adders,” Journal of Intelligent Procedures in Electrical Technology (JIPET), vol. 10, no. 33, pp. 13-22, May 2019, dor: 20.1001.1.23223871.1398.10.37.2.6.
[8] A. B. Rahin, A. Kadivarian and V. B. Rahin, “Design of a Full Swing 20-Transistors Full Adder Cell based on CNTFET with High Speed and Low PDP,” 30th International Conference on Electrical Engineering (ICEE), 2022, pp. 546-550, doi: 10.1109/ICEE55646.2022.9827050.
[9] A. Baghi Rahin and V. Baghi Rahin, “FinFET-based Full Adder using SDTSPC Logic with High Performance,” International Journal of Mechatronics Electrical and Computer Technology (IJMEC), vol. 10, no. 38, pp. 4773-4778, 2020.
[10] A. Baghi Rahin, A. Kadivarian and V. Baghi Rahin, “CNTFET-based Full Adder with Ultra Low-Power and PDP for Mobile Applications,” 5th Conference on Technology In Electrical and Computer Engineering (ETECH 2020), 2020.
[11] A. Baghi Rahin, A. Kadivarian, S. Naseri Akbar and V. Baghi Rahin, “High-Speed and Low-Voltage 16-T Dynamic Full Adder Cell Based on FinFET Transistors,” International Conference on New Researches and Technologies in Electrical Engineering (ICNRTEE), At: University of Science and Culture (USC), Tehran, Iran, 2023.
[12] L. Abdelaziz, B. Khaled and G. Mustapha, “Design, Analysis and Optimization of CMOS Full Adder Based FinFET 10 nm,” 13th International Symposium on Advanced Topics in Electrical Engineering (ATEE), Bucharest, Romania, 2023, pp. 1-5, doi: 10.1109/ATEE58038.2023.10108377.
[13] A. Sadeghi, R. Ghasemi, H. Ghasemian and N. Shiri, "High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures," in IEEE Embedded Systems Letters, vol. 15, no. 1, pp. 33-36, March 2023, doi: 10.1109/LES.2022.3192530.
[14] P. -M. Lee, C. -H. Hsu and Y. -H. Hung, "Novel 10-T full adders realized by GDI structure," 2007 International Symposium on Integrated Circuits, Singapore, 2007, pp. 115-118, doi: 10.1109/ISICIR.2007.4441810.
[15] G. Park and Y. Kim, "Low Power Gate Diffusion Input Full Adder using Floating Body," 2021 18th International SoC Design Conference (ISOCC), Jeju Island, Korea, Republic of, 2021, pp. 337-338, doi: 10.1109/ISOCC53507.2021.9613966.
[16] I. Hassoune, D. Flandre, I. O'Connor and J. -D. Legat, “ULPFA: A New Efficient Design of a Power-Aware Full Adder,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 8, pp. 2066-2074, Aug. 2010, doi: 10.1109/TCSI.2008.2001367.
[17] A. Morgenshtein, A. Fish and I. A. Wagner, “Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 5, pp. 566-581, Oct. 2002, doi: 10.1109/TVLSI.2002.801578.
[18] R. Uma and P. Dhavachelvan, “Modified Gate Diffusion Input Technique: A New Technique for Enhancing Performance in Full Adder Circuits,” Procedia Technology, vol. 6, pp. 74-81, 2012, doi:10.1016/j.protcy.2012.10.010.
[19] V. Foroutan, M.R. Taheri, K. Navi and A. Azizi Mazreah, “Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style,” Integration,the VLSI journal, vol. 47, no. 1, 2014, pp. 48-61, doi: 10.1016/j.vlsi.2013.05.001.
[20] M. Shoba and R. Nakkeeran, “GDI based full adders for energy efficient arithmetic applications,” Engineering Science and Technology, an International Journal, vol. 19, no. 1, pp. 485-496, 2016, doi: 10.1016/j.jestch.2015.09.006.
[21] J. M. Rabey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuit, A Design Perspective, Englewood Cliffs, NJ: Prentice Hall, 2002 .
[22] A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky and A. Fish, “Full-Swing Gate Diffusion Input logic—Case-study of low-power CLA adder design,” Integration,the VLSI journal, vol. 47, no. 1, pp. 62-70, 2014, doi: 10.1016/j.vlsi.2013.04.002.
[23] J. Shrivas, S. Akashe and N. Tiwari, “Design and performance analysis of 1 bit full adder using GDI technique in nanometer era,” World Congress on Information and Communication Technologies, 2012, pp. 822-825, doi: 10.1109/WICT.2012.6409188.
[24] G. A. Katopis, “Delta-I noise specification for a high-performance computing machine,” in Proceedings of the IEEE, vol. 73, no. 9, pp. 1405-1415, Sept. 1985, doi: 10.1109/PROC.1985.13301.
[25] G. Balamurugan and N. R. Shanbhag, “The twin-transistor noise-tolerant dynamic circuit technique,” in IEEE Journal of Solid-State Circuits, vol. 36, no. 2, pp. 273-280, Feb. 2001, doi: 10.1109/4.902768.
_||_[1] M. Sayyaf, A. Ghasemi, R. Hamzehyan, “Design of Low Power Single-Bit Full-Adder Cell Based on Pass-Transistor Logic,” Journal of Southern Communication Engineering, Articles in Press, Accepted Manuscript, Available Online from 14 July 2022, doi: 10.30495/jce.2022.692834 (in Persian).
[2] T. Rashedzadeh, S. M. A. Riyazi, N. Cheraghi Shirazi, “Analysis of the effect of changes of FINs Architectural on FINFET Drain current and on Average Power Dissipation and Propagation Delay in the Hybrid-CMOS full adder,” Journal of Southern Communication Engineering, vol. 10, no. 40, pp. 25-36, July 2021, (in Persian).
[3] A. Baghi Rahin and V. Baghi Rahin, “Ultra low voltage and low power 4-2 compressor using FinFET transistors,” Journal of Intelligent Procedures in Electrical Technology (JIPET), vol. 9, no. 33, pp. 25-36, May 2018, dor: 20.1001.1.23223871.1397.9.33.3.2.
[4] K. L. Shepard, “Design methodologies for noise in digital integrated circuits,” Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175), 1998, pp. 94-99, doi: 10.1145/277044.277062.
[5] N. Eshraghian, and K. Weste, Principles of CMOS VLSI Design. A System Perspective. Reading, MA: Addison-Wesley., 1993
[6] SIA National Technology Roadmap for Semiconductors. SE-MATECH, Inc., 1997.
[7] A. Baghi Rahin and V. Baghi Rahin, “A New 2-input CNTFET-Based XOR Cell With Ultra-Low Leakage Power For Low-Voltage and Low-Power Full Adders,” Journal of Intelligent Procedures in Electrical Technology (JIPET), vol. 10, no. 33, pp. 13-22, May 2019, dor: 20.1001.1.23223871.1398.10.37.2.6.
[8] A. B. Rahin, A. Kadivarian and V. B. Rahin, “Design of a Full Swing 20-Transistors Full Adder Cell based on CNTFET with High Speed and Low PDP,” 30th International Conference on Electrical Engineering (ICEE), 2022, pp. 546-550, doi: 10.1109/ICEE55646.2022.9827050.
[9] A. Baghi Rahin and V. Baghi Rahin, “FinFET-based Full Adder using SDTSPC Logic with High Performance,” International Journal of Mechatronics Electrical and Computer Technology (IJMEC), vol. 10, no. 38, pp. 4773-4778, 2020.
[10] A. Baghi Rahin, A. Kadivarian and V. Baghi Rahin, “CNTFET-based Full Adder with Ultra Low-Power and PDP for Mobile Applications,” 5th Conference on Technology In Electrical and Computer Engineering (ETECH 2020), 2020.
[11] A. Baghi Rahin, A. Kadivarian, S. Naseri Akbar and V. Baghi Rahin, “High-Speed and Low-Voltage 16-T Dynamic Full Adder Cell Based on FinFET Transistors,” International Conference on New Researches and Technologies in Electrical Engineering (ICNRTEE), At: University of Science and Culture (USC), Tehran, Iran, 2023.
[12] L. Abdelaziz, B. Khaled and G. Mustapha, “Design, Analysis and Optimization of CMOS Full Adder Based FinFET 10 nm,” 13th International Symposium on Advanced Topics in Electrical Engineering (ATEE), Bucharest, Romania, 2023, pp. 1-5, doi: 10.1109/ATEE58038.2023.10108377.
[13] A. Sadeghi, R. Ghasemi, H. Ghasemian and N. Shiri, "High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures," in IEEE Embedded Systems Letters, vol. 15, no. 1, pp. 33-36, March 2023, doi: 10.1109/LES.2022.3192530.
[14] P. -M. Lee, C. -H. Hsu and Y. -H. Hung, "Novel 10-T full adders realized by GDI structure," 2007 International Symposium on Integrated Circuits, Singapore, 2007, pp. 115-118, doi: 10.1109/ISICIR.2007.4441810.
[15] G. Park and Y. Kim, "Low Power Gate Diffusion Input Full Adder using Floating Body," 2021 18th International SoC Design Conference (ISOCC), Jeju Island, Korea, Republic of, 2021, pp. 337-338, doi: 10.1109/ISOCC53507.2021.9613966.
[16] I. Hassoune, D. Flandre, I. O'Connor and J. -D. Legat, “ULPFA: A New Efficient Design of a Power-Aware Full Adder,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 8, pp. 2066-2074, Aug. 2010, doi: 10.1109/TCSI.2008.2001367.
[17] A. Morgenshtein, A. Fish and I. A. Wagner, “Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 5, pp. 566-581, Oct. 2002, doi: 10.1109/TVLSI.2002.801578.
[18] R. Uma and P. Dhavachelvan, “Modified Gate Diffusion Input Technique: A New Technique for Enhancing Performance in Full Adder Circuits,” Procedia Technology, vol. 6, pp. 74-81, 2012, doi:10.1016/j.protcy.2012.10.010.
[19] V. Foroutan, M.R. Taheri, K. Navi and A. Azizi Mazreah, “Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style,” Integration,the VLSI journal, vol. 47, no. 1, 2014, pp. 48-61, doi: 10.1016/j.vlsi.2013.05.001.
[20] M. Shoba and R. Nakkeeran, “GDI based full adders for energy efficient arithmetic applications,” Engineering Science and Technology, an International Journal, vol. 19, no. 1, pp. 485-496, 2016, doi: 10.1016/j.jestch.2015.09.006.
[21] J. M. Rabey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuit, A Design Perspective, Englewood Cliffs, NJ: Prentice Hall, 2002 .
[22] A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky and A. Fish, “Full-Swing Gate Diffusion Input logic—Case-study of low-power CLA adder design,” Integration,the VLSI journal, vol. 47, no. 1, pp. 62-70, 2014, doi: 10.1016/j.vlsi.2013.04.002.
[23] J. Shrivas, S. Akashe and N. Tiwari, “Design and performance analysis of 1 bit full adder using GDI technique in nanometer era,” World Congress on Information and Communication Technologies, 2012, pp. 822-825, doi: 10.1109/WICT.2012.6409188.
[24] G. A. Katopis, “Delta-I noise specification for a high-performance computing machine,” in Proceedings of the IEEE, vol. 73, no. 9, pp. 1405-1415, Sept. 1985, doi: 10.1109/PROC.1985.13301.
[25] G. Balamurugan and N. R. Shanbhag, “The twin-transistor noise-tolerant dynamic circuit technique,” in IEEE Journal of Solid-State Circuits, vol. 36, no. 2, pp. 273-280, Feb. 2001, doi: 10.1109/4.902768.
