طراحی سلول تمام جمع کننده تک بیتی کم توان مبتنی بر ترانزیستور عبور
محورهای موضوعی : مهندسی الکترونیک
مهدی سیاف
1
(گروه برق، واحد بوشهر، دانشگاه آزاد اسلامی، بوشهر، ایران)
عبدالرسول قاسمی
2
(گروه برق، واحد بوشهر، دانشگاه آزاد اسلامی، بوشهر، ایران)
روزبه حمزه ئیان
3
(گروه برق، واحد بوشهر، دانشگاه آزاد اسلامی بوشهر، ایران)
کلید واژه: ترانزیستور عبور, تمام‌جمع‌کننده, حداقل تاخیر, کم توان,
چکیده مقاله :
در دنیای الکترونیک و دیجیتال امروزی، افزایش تقاضا برای سیستم‌های قابل حمل موجب شده تا صنعت الکترونیک و تکنولوژی طراحی تراشه‌ها به سمت روش‌های کاهش مصرف توان سوق پیدا کنند و لذا مصرف توان به معیاری مهم در این زمینه تبدیل شده است. هم‌چنین افزایش سرعت تراشه‌ها و کاهش تاخیر انتشار مدارها همواره از اهداف مهم مهندسان طراح دیجیتال بوده است. از انجا که عنصر جمع‌کننده از جمله عناصر مهم در بسیاری از سیستم‌های دیجیتال است، لذا امروزه جمع‌کننده‌های گوناگون با تکنولوژی‌ها و رویکردهای مختلف طراحی مطرح شده‌اند که هر یک دارای مزایا و معایب مشخصی می‌باشند. در این مقاله، سلول مدار تمام جمع کننده تک بیتی مبتنی بر ترانزیستور عبور با مصرف توان کم ارائه شده است این مدار با فرکانس 1GHZبرای استفاده در بلوک های واحد محاسبه منطق و ریاضی پردازنده‌های سیگنال دیجیتال و انواع سیستم‌های الکترونیکی و مخابراتی دیجیتال کاربرد دارد . در مدار پیشنهادی از ساختار XOR-XOR استفاده شده و مبتنی بر تکنینک ترانزیستور عبور می باشد و پارامترهایی نظیر توان مصرفی، تاخیر انتشار، حاصلضرب توان در تاخیر ، و تعداد ترانزیستورها بهبود حاصل شده است. مدار پیشنهادی در تکنولوژی 180نانومتر CMOS طراحی شده است و نتایج شبیه سازی نشان می دهد که به ازای ولتاژ تغذیه 1.8 ولت توان مصرفی برابر با 83 میکرو وات ، تاخیر زمانی 89 پیکو ثانیه ، حاصلضرب توان در تاخیر 7 فمتو ژول بدست می آید.
In today's electronic and digital world, increasing demand for portable systems has led the electronics industry and chip design technology to reduce power consumption methods, and therefore power consumption has become an important criterion in this field. Also, increasing the speed of chips and reducing the propagation delay of circuits has always been an important goal of digital design engineers. Since the Adder element is one of the important elements in many digital systems, so today various Adders with different technologies and design approaches have been proposed, each of which has certain advantages and disadvantages. This paper presents a low-power single-bit full-adder cell design that is based on pass-transistor logic.This circuit is used in the arithmetic logic units of digital signal processors and also in several electronic and digital communication systems that operate within the frequency range of in 1GHz. The proposed cell exploits the pass transistor techniques and XOR-XOR structures to improve the design parameters namely power consumption, propagation delay, power–delay product, and the number of transistors. The proposed circuit is designed using 180nm CMOS technology and the simulation results show that for a supply voltage of 1.8V, the power consumption, delay, and power–delay product have been achieved as 83 W, 89ps, and 7fJ respectively.
[1] Y. Safaei Mehrabani and M. Eshghi, "Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 11, pp. 3268-3281, Nov. 2016, doi: 10.1109/TVLSI.2016.2540071.
[2] M. Keerthana and T. Ravichandran, "Implementation of Low Power 1-bit Hybrid Full Adder using 22 nm CMOS Technology," 2020 6th International Conference on Advanced Computing and Communication Systems (ICACCS), 2020, pp. 1215-1217, doi: 10.1109/ICACCS48705.2020.9074256.
[3] M. A. Chowdhury, M. A. Mona, A. Al Asif, M. Nayem, M. A. Z. Dipto and A. Sorwar, "Performance Comparison of Full Adder Cells in 45nm Technology Node," 2021 International Conference on Computer Communication and Informatics (ICCCI), 2021, pp. 1-5, doi: 10.1109/ICCCI50826.2021.9402506.
[4] O. A. Badry and M. A. Abdelghany, "Low power 1-Bit full adder using Full-Swing gate diffusion input technique," 2018 International Conference on Innovative Trends in Computer Engineering (ITCE), 2018, pp. 205-208, doi: 10.1109/ITCE.2018.8316625.
[5] A. N. M. Hossain and M. A. Abedin, "Implementation of an XOR Based 16-bit Carry Select Adder for Area, Delay and Power Minimization," 2019 International Conference on Electrical, Computer and Communication Engineering (ECCE), 2019, pp. 1-4, doi: 10.1109/ECACE.2019.8679293.
[6] K. Himabindu and K. Hariharan, "Design of area and power efficient full adder in 180nm," 2017 International Conference on Networks & Advances in Computational Technologies (NetACT), 2017, pp. 336-340, doi: 10.1109/NETACT.2017.8076791.
[7] T. Nikoubin, O. Kavehie and K. Navi, “A New Design for 6 Transistors XOR / XNOR, Based on High-Speed and Low-Power Arithmetic Circuits Chains Design,” International conference on computer society of Iran , Tehran, 2006, pp. 930-923.
[8] J.M. Wang, S.C. Fang and W.S. Feng, "New efficient designs for XOR and XNOR functions on the transistor level," in IEEE Journal of Solid-State Circuits, vol. 29, no. 7, pp. 780-786, July 1994, doi: 10.1109/4.303715.
[9] V. Moalemi and A. Afzali-Kusha, "Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies," IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007, pp. 514-515, doi: 10.1109/ISVLSI.2007.93.
_||_[1] Y. Safaei Mehrabani and M. Eshghi, "Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 11, pp. 3268-3281, Nov. 2016, doi: 10.1109/TVLSI.2016.2540071.
[2] M. Keerthana and T. Ravichandran, "Implementation of Low Power 1-bit Hybrid Full Adder using 22 nm CMOS Technology," 2020 6th International Conference on Advanced Computing and Communication Systems (ICACCS), 2020, pp. 1215-1217, doi: 10.1109/ICACCS48705.2020.9074256.
[3] M. A. Chowdhury, M. A. Mona, A. Al Asif, M. Nayem, M. A. Z. Dipto and A. Sorwar, "Performance Comparison of Full Adder Cells in 45nm Technology Node," 2021 International Conference on Computer Communication and Informatics (ICCCI), 2021, pp. 1-5, doi: 10.1109/ICCCI50826.2021.9402506.
[4] O. A. Badry and M. A. Abdelghany, "Low power 1-Bit full adder using Full-Swing gate diffusion input technique," 2018 International Conference on Innovative Trends in Computer Engineering (ITCE), 2018, pp. 205-208, doi: 10.1109/ITCE.2018.8316625.
[5] A. N. M. Hossain and M. A. Abedin, "Implementation of an XOR Based 16-bit Carry Select Adder for Area, Delay and Power Minimization," 2019 International Conference on Electrical, Computer and Communication Engineering (ECCE), 2019, pp. 1-4, doi: 10.1109/ECACE.2019.8679293.
[6] K. Himabindu and K. Hariharan, "Design of area and power efficient full adder in 180nm," 2017 International Conference on Networks & Advances in Computational Technologies (NetACT), 2017, pp. 336-340, doi: 10.1109/NETACT.2017.8076791.
[7] T. Nikoubin, O. Kavehie and K. Navi, “A New Design for 6 Transistors XOR / XNOR, Based on High-Speed and Low-Power Arithmetic Circuits Chains Design,” International conference on computer society of Iran , Tehran, 2006, pp. 930-923.
[8] J.M. Wang, S.C. Fang and W.S. Feng, "New efficient designs for XOR and XNOR functions on the transistor level," in IEEE Journal of Solid-State Circuits, vol. 29, no. 7, pp. 780-786, July 1994, doi: 10.1109/4.303715.
[9] V. Moalemi and A. Afzali-Kusha, "Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies," IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007, pp. 514-515, doi: 10.1109/ISVLSI.2007.93.
