List of Articles Ternary Half Adder

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  1 - High-Speed Ternary Half adder based on GNRFET
  Mahdieh Nayeri Peiman Keshavarzian Maryam Nayeri
  10.22034/jna.2019.1865874.1138
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• Open Access Article
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  2 - High-Speed Ternary Half adder based on GNRFET
  Mahdieh Nayeri Peiman Keshavarzian Maryam Nayeri
  10.22034/jna.2019.668030
  Manuscript profile
• Open Access Article
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  3 - Ternary DCVS Half Adder with Built-in Boosters
  Naghmeh Dehabadi Reza Faghih Mirzaee
  Differential Cascode Voltage Switch (DCVS) is one of the most well-known logic styles, which forms a robust structure. In addition, two complementary outputs are produced in this logic style at the same time. It has several unique attributes and different applications. More

  Differential Cascode Voltage Switch (DCVS) is one of the most well-known logic styles, which forms a robust structure. In addition, two complementary outputs are produced in this logic style at the same time. It has several unique attributes and different applications. This paper presents three comparable methods to design some ternary half adders, whose efficiencies are superior especially when they are put one after another in a cascading scenario. These cells are essential for the realization of larger arithmetic circuits. In the third proposed method, instead of ternary inverters, which consume considerable static power, built-in low-power binary boosters are exploited to reinforce driving power of the DCVS circuits. Simulation results by HSPICE and 32 nm Carbon Nanotube Field Effect Transistor (CNFET) technology demonstrate that the new adder cell with binary boosters operates 21.8% faster and consume 6.7% less power than the cell with ternary inverters in a real test bed. Furthermore, the final design is compared with three other ternary half adders. The new design is faster than all of them, and also consumes less power and energy than the previous DCVS half adder. Manuscript profile