The share of static power from the total consumed power in deep submicron circuits is rapidly rising due to short channel effects. The present paper examines the recent techniques introduced for reducing leakage power and proposes a novel technique based on switched-capacitor (SC) circuits for this purpose. The central concept consists of using two SCs on the route to PUN and PDN up to the output. Very high temperature stability and the ability to control the SC circuits using the clock frequency (〖 f〗_c) are among the benefits of the proposed concept. The introduced technique was implemented on NAND, NOR, and XOR logic gates and the C17 standard circuit. Next, the proposed model was simulated in HSPICE software with 32-nm BSIM4 (level-54 parameters) CMOS technology to investigate its leakage power, delay, surface area, and PDP factors. The results indicate the excellent leakage power reduction performance of this technique compared to previously introduced techniques. Implementing the presented circuit in various corners of the process and a subsequent temperature stability analysis demonstrated the high reliability of the proposed technique. Manuscript profile