Increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. NoCs have features such as scalability and high performance. NoCs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made NoC. Due to increasing number of cores, the placement of the cores in NoC platform has become an important issue. If wecan map the application cores close to each other to place them with more communication requirements, the performance parameters will improve and the network will be more efficient. Inthis paper, we propose two low complexity heuristic algorithms for the application mapping onto NoC to improve latency. In addition, one approach has been proposed to extract an Abstract graph from an application core graph, so, using this resent approach, we can map applications in two proposed algorithms. Moreover, we use bypass routers that can route packets in a cycle from the source to destination. Proposed algorithms and previous papers were compared on two real applications VOPD and MPEG-4 and results were reported. Manuscript profile

By increasing, the complexity of chips and the need to integrating more components into a chip has made network on- chip known as an important infrastructure for network communications on the system, and is a good alternative to traditional ways and using the bus. By increasing the density of chips, the possibility of failure in the chip network increases and providing correction and fault tolerance methods is one of the principles of today's chip design. Faults may have undesirable effects on the correct system operation and system performance. In this paper the communication infrastructure failure has been considered as same as link and router failure and the fault tolerance low cost routing algorithm has been suggested base on local fault information By using quad neighbor fault information to avoid back tracking in routing in order to select possible minimal path to destination. In this article, we have suggested cost aware fault tolerance (CAFT) routing algorithm. Our contribution in this algorithm is minimum local fault information, minimum routing decision overhead by implementing routing logic base and determining shortest possible path. For deadlock freedom using an additional virtual channel along Y dimension and prohibiting certain routing turns. In order to evaluate the performance of our routing, we compared it with other fault tolerant routing in terms of average packet latency, throughput and power. Manuscript profile

We design and simulate a five-port optical router, which is composed of twenty Mach-Zehnder-based switching elements and twelve waveguide crossings for use in integrated photonic interconnection networks. We simulated and analyzed the operation of the proposed optical router from the aspects of insertion loss,power budget, Q-factor and the minimum bit error ratio by use of OptiSystem simulator. The simulation results show that twenty possible input/output routing paths of the five-port optical router are verified at a data transmission rate of 20 Gbps for all input-output channels. Manuscript profile