In communication systems, ensuring correct information reception is very important, Error Correction Coding methods have been developed in order to achieve this goal. Convolutional Code is used in Wireless, Satellite, mobile phones and Deep-Space communications, it is one of the most powerful Error Correction code, and the Viterbi algorithm is robust way to decode it. Power conception and speed are two important feature of Viterbi decoders, in many communications the power consumption is most important. In this paper, by removing extra decoding cycles, the SMU registers are reduced by 20%, the power consumption reduced by 14.5% and the speed increased 6 times without error correction performance loss. The proposed design is described by VHDL and it is implemented on Xilinx Spartan3, Xc3s400 FPGA chip. Manuscript profile

P. Elias proposed convolutional coding at 1955. Convolutional encoders have very simple structure but their decoders are very complex and power consumer. Power consumption and error correction of Convolutional Codes, will be enhanced by increase in their constrain length, therefore there is always a trade-off between Power consumption and error correction. In Convolutional Codes, the code specifications remain constant in each frame. If the specifications are changed during each frame in a code, a new code with new performance and specifications is created. This paper, aims to evaluate this issue for the first time and compare its performance with Convolutional Codes. This new code is named “Decimal Convolutional”. If in a decimal convolutional code, constrain length is changed during each frame, the generated code will be a convolutional code with “decimal constrain length”. In this paper, a convolutional code with decimal constrain length is introduced, encoder and Viterbi decoder structure is explained for it and its specification is compared with convolutional code. Using this code, an optimized constrain length can be obtained and relative power consumption of decoder can be also reduced. The proposed design blocks are described by VHDL and they are implemented on Xilinx Spartan3, Xc3s400 FPGA chip. Manuscript profile