Design and Simulation of a New Capacitance Multiplier with Adaptive Current Bias and Quasi-Floating Gate Technique with Electronic Tunability and High Linearity for Biomedical Applications

Subject Areas : Electronic integrated circuits

Mohammad Aghaei Jeshvaghani ¹ ( Department of Electrical Engineering- Najafabad Branch, Islamic Azad University, Najafabad, Iran )
Mehdi Dolatshahi ² ( Department of Electrical Engineering- Najafabad Branch, Islamic Azad University, Najafabad, Iran )
Sayed Mohammad Ali Zanjani ³ ( Smart Microgrid Research Center- Najafabad Branch, Islamic Azad University, Najafabad, Iran )
Mohammad Amin Honarvar ⁴ ( Smart Microgrid Research Center- Najafabad Branch, Islamic Azad University, Najafabad, Iran )

Received: 2022-07-23 Accepted : 2022-11-28 Published : 2025-02-19

Keywords: Linearity, Biomedical, capacitance multipliers, adaptive current, Electronic adjustability,

Abstract :

Employing capacitance multipliers in low-frequency integrated circuits has a significant effect on reducing the chip size area. The main idea behind the proposed circuit in this paper is to use a folded current follower (FCF) structure to effectively reduce the equivalent series resistance (ESR) in the input stage. Furthermore, using an auxiliary circuit to adapt the bias current of the transistors and applying the necessary signals by the quasi-floating gate technique (QFG), are other approaches employed to reduce the static power consumption while properly increasing the linearity of the proposed circuit, which can be considered as other benefits of the proposed approach. On the other hand, to improve the linearity, negative feedback is used and necessary voltage is applied to the gate of the transistors in the current sampler. The “K” coefficient can be adjusted by the active method. Low input resistance and high output resistance as well as the reduced occupied silicon area are achieved based on the simulation results of the proposed circuit. The simulation results in 0.18 μm technology show that, with a 0.8 V power supply and base capacitor (Cb=1 pF), for 850 nW power consumption, a capacitor equivalent to 204 pF is achieved in the proposed approach. As another example, to realize the 101 pF capacitor with the supply as mentioned above and base capacitor, the proposed multiplier requires 6.3 times less area and 23 times more bandwidth than FCF, which shows the increased accuracy of the proposed design. In the proposed circuit, in the presence of a current adaptive circuit with an input signal range of 7 nA, the output current range is obtained as 1510 nA, While the output bias current is 100nA and the harmonic distortion value is obtained as 3.6%. The proposed circuit has the highest figure of merit 42.823 MHz/μW, which shows superiority in overall performance in comparison with other reported designs.

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