Using Chip Master Planning in Automatic ASIC Design Flow to Improve Performance and Buffer Resource Management
Subject Areas : Journal of Computer & RoboticsAli Jahanian 1 , Morteza Saheb Zamani 2
1 - Department of Electrical and Computer Engineering, Shahid Beheshti University, G. C., Tehran, Iran
2 - IT and Computer Engineering Department, Amirkabir University of Technology, Tehran, Iran
Keywords:
Abstract :
[1] H.M. Chen, H. Zhou, F.Y. Young, D.F. Wong, H.H. Yang, and N. Sherwani, Integrated floorplanning and interconnect planning, In Proc. of Int. Conf. on Computer Aided Design, pp.354-357, 1999.
Table 4
Experimental results for the conventional buffer insertion flow and BMPBI flow Circuit WSR Conventional buffer insertion flow BMP-based buffer insertion flow (BMPBI) PDP Reduction CPU Time Overhead #buffs Delay (ps) PDP Avg. PDP CPU time (sec) #buffs Delay (ps) PDP Avg. PDP CPU time (sec) des_area 15% 27 1598 23298.84 17716.3 5.1 14 1587 11997.72 15232.92 5.3 1.4% 3% 10% 19 1578 16190.28 13 1602 11246.04 3% 16 1581 13659.84 26 1600 22464 systemaes 15% 10 2203 11896.2 13060.7 10.7 9 2230 10837.8 10597.32 11.1 2.3% 3% 10% 14 2193 16579.08 9 2203 10706.58 3% 9 2203 10706.58 9 2203 10706.58 tv80 15% 39 2364 49764.8 46312.1 11 22 2366 28108 42096.4 11.4 9.1% 3% 10% 41 2355 52135.7 24 2365 37035.9 3% 29 2365 37035.9 48 2359 61145.3 ac97_ctrl 15% 11 823 4888.6 3780.8 14 7 834 3152.5 3477.5 14.5 8.02% 3% 10% 6 825 2673 9 819 3980 3% 7 FAILED - 4 825 3300 dma 15% 133 2667 191543.9 192498.9 26.3 127 2706 185577.4 166114.66 27 13.7% 5.7% 10% 138 2596 193454 99 2712 144983.5 3% 263 FAILED - 119 2611 167782.8 aes_core 15% 18 1400 25200 31711.3 20.3 19 1390 26410 20496.66 21.7 35% 5.5% 10% 19 1390 26410 22 1340 29480 3% 31 1404 43524 4 1400 5600 Average 11.58% 3.86%
Journal of Computer & Robotics 1 (2010) 125-135
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