Design and Realization of a Junction-less TFET for Analog and Digital Applications Based on Strain Engineering
Subject Areas : Majlesi Journal of Telecommunication Devices
Fayzollah
Khorramrouze
1
(Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran.)
Seyed Ali
Sedigh Ziabari
2
(Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran.)
Ali
Heydari
3
(Department of Electrical Engineering, Guilan University, Rasht, Ira)
Keywords:
Abstract :
[1] W. Y. Choi, B. G. Park, J. D. Lee, and T. J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 743–745, 2007.
[2] M. Rahimian and M. Fathipour, “N-P-N Bipolar Action in Junctionless Nanowire TFET : Physical Operation of a Modified Current Mechanism for Low Power Applications,” no. August, pp. 1–24, 2016.
[3] D. B. Abdi and M. J. Kumar, “Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain,” IEEE J. Electron Devices Soc., vol. 2, no. 6, pp. 187–190, 2014.
[4] K. K. K and B. R. N, “Sub-threshold Leakage Current Reduction Using Variable Gate Oxide Thickness ( VGOT ) MOSFET,” vol. 2, no. 2, pp. 24–28, 2013.
[5] P. K. Asthana, B. Ghosh, Y. Goswami, B. Mukund, and M. Tripathi, “High-Speed and Low-Power Ultradeep-Submicrometer III – V Heterojunctionless,” IEEE Trans. Electron Devices, vol. 61, no. 2, pp. 479–486, 2014.
[6] S. B. Rahi, P. Asthana, and S. Gupta, “Heterogate junctionless tunnel field-effect transistor: future of low-power devices,” J. Comput. Electron., vol. 16, no. 1, pp. 30–38, 2017.
[7] S. B. Rahi, B. Ghosh, and P. Asthana, “A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET,” J. Semicond., vol. 35, no. 11, 2014.
[8] X. Liu et al., “Study of novel junctionless Ge n-Tunneling Field-Effect Transistors with lightly doped drain (LDD) region,” Superlattices Microstruct., vol. 102, no. 2, pp. 7–16, 2017.
[9] A. C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS logic,” Proc. IEEE, vol. 98, no. 12, pp. 2095–2110, 2010.
[10] K. Boucart and A. M. Ionescu, “Double-gate tunnel FET with high-K gate dielectric,” IEEE Trans. Electron Devices, vol. 54, no. 7, pp. 1725–1733, 2007.
[11] H. Aghandeh, S. Ali, and S. Ziabari, “Gate engineered heterostructure junctionless TFET with Gaussian doping pro fi le for ambipolar suppression and electrical performance improvement,” Superlattices Microstruct., pp. 1–12, 2017.
[12] R. Molaei Imen Abadi and S. A. Sedigh Ziabari, “Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach,” Appl. Phys. A Mater. Sci. Process., vol. 122, no. 11, pp. 1–9, 2016.
[13] Y. Goswami, P. Asthana, and B. Ghosh, “Nanoscale III–V on Si-based junctionless tunnel transistor for EHF band applications,” J. Semicond., vol. 38, no. 5, p. 054002, 2017.
[14] J. Schulze et al., “Vertical Ge and GeSn heterojunction gate-all-around tunneling field effect transistors,” Solid. State. Electron., vol. 110, pp. 59–64, 2015.
[15] H. D. Tsague and B. Twala, “Simulation and parameter optimization of polysilicon gate biaxial strained silicon MOSFETs,” 2015 5th Int. Conf. Digit. Inf. Process. Commun. ICDIPC 2015, pp. 38–43, 2015.
[16] M. Najmzadeh, L. De Michielis, D. Bouvet, P. Dobrosz, S. Olsen, and A. M. Ionescu, “Silicon nanowires with lateral uniaxial tensile stress profiles for high electron mobility gate-all-around MOSFETs,” Microelectron. Eng., vol. 87, no. 5–8, pp. 1561–1565, 2010.
[17] S. Takagi, M. Kim, M. Noguchi, S. M. Ji, K. Nishi, and M. Takenaka, “III-V and Ge/strained SOI tunneling FET technologies for low power LSIs,” Dig. Tech. Pap. - Symp. VLSI Technol., vol. 2015–Augus, no. 2011, pp. T22–T23, 2015.
[18] S. Takagi and M. Takenaka, “Ge/III-V MOS device technologies for low power integrated systems,” Eur. Solid-State Device Res. Conf., vol. 2015–Novem, pp. 20–25, 2015.
[19] M. K. Moghadam and S. E. Hosseini, “Investigation of a SiGe Tunnel FET : Comparison to Si and Ge TFETs,” J. Electr. Syst. Signals, vol. 2, no. 1, pp. 21–25, 2014.
[20] M. Visciarelli, E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, “Impact of Strain on Tunneling Current and Threshold Voltage in III-V Nanowire TFETs,” IEEE Electron Device Lett., vol. 37, no. 5, pp. 560–563, 2016.
[21] T. A. Langdo et al., “SiGe-free strained Si on insulator by wafer bonding and layer transfer,” Appl. Phys. Lett., vol. 82, no. 24, pp. 4256–4258, 2003.
[22] C. Grillet, D. Logoteta, A. Cresti, and M. G. Pala, “Assessment of the Electrical Performance of Short Channel InAs and Strained Si Nanowire FETs,” IEEE Trans. Electron Devices, vol. 64, no. 5, pp. 2425–2431, 2017.
[23] S. Saurabh and M. J. K. Ã, “Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor : Theoretical Investigation and Analysis Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect T,” vol. 064503, no. 064503, pp. 1–35.
[24] Q. T. Zhao, J. M. Hartmann, and S. Mantl, “An Improved Si Tunnel Field Effect Transistor With a Buried Strained Si(1-x)Ge(x),” IEEE Electron Device Lett., vol. 32, no. 11, pp. 1480–1482, 2011.
[25] M. Kumar and S. Jit, “Effects of Electrostatically Doped Source/Drain and Ferroelectric Gate Oxide on Subthreshold Swing and Impact Ionization Rate of Strained-Si-on-Insulator Tunnel Field-Effect Transistors,” IEEE Trans. Nanotechnol., vol. 14, no. 4, pp. 597–599, 2015.
[26] Q. T. Zhao et al., “Strained Si and SiGe nanowire tunnel FETs for logic and analog applications,” IEEE J. Electron Devices Soc., vol. 3, no. 3, pp. 103–114, 2015.
[27] M. J. Kumar and S. Saurabh, “Tunnel Field Effect Transistor (TFET) with strained silicon thinfilm body for enhanced drain current and pragmatic threshold voltage,” 2008 NSTI Nanotechnol. Conf. Trade Show, NSTI Nanotech 2008 Jt. Meet. Nanotechnol. 2008, June 1, 2008 - June 5, 2008, vol. 3, pp. 28–30, 2008.
[28] D. K. Dash, P. Saha, and S. K. Sarkar, “Analytical modeling of asymmetric hetero-dielectric engineered dual-material DG-TFET,” J. Comput. Electron., vol. 17, no. 1, pp. 181–191, Mar. 2018.
[29] S. Kumar and B. Raj, “Compact channel potential analytical modeling of DG-TFET based on Evanescent-mode approach,” J. Comput. Electron., vol. 14, no. 3, pp. 820–827, Sep. 2015.
[30] S. Kumar, E. Goel, K. Singh, B. Singh, M. Kumar, and S. Jit, “A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors with a SiO2/High-k Stacked Gate-Oxide Structure,” IEEE Trans. Electron Devices, vol. 63, no. 8, pp. 3291–3299, Aug. 2016.
[31] R. Vishnoi and M. J. Kumar, “2-D analytical model for the threshold voltage of a tunneling FET with localized charges,” IEEE Trans. Electron Devices, vol. 61, no. 9, pp. 3054–3059, Sep. 2014.
[32] P. Palestri and C. Press, Nanoscale MOS transistors: Semi-classical modeling and applications. Cambridge University Press, 2014.
[33] M. J. Kumar, V. Venkataraman, and S. Nawal, “Analytical drain current model of nanoscale strained-Si/SiGe MOSFETs for analog circuit simulation,” in Proceedings of the IEEE International Conference on VLSI Design, 2007, pp. 189–194.
[34] S. Sharma, “An Analysis of Device Characteristics of Strained N-Channel MOSFET,” vol. 3, no. 8, pp. 87–90, 2016.
[35] P. Pandey, R. Vishnoi, and M. J. Kumar, “A full-range dual material gate tunnel field effect transistor drain current model considering both source and drain depletion region band-to-band tunneling,” J. Comput. Electron., vol. 14, no. 1, pp. 280–287, Mar. 2015.
[36] J. S. Lim, S. E. Thompson, and J. G. Fossum, “Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs,” IEEE Electron Device Lett., vol. 25, no. 11, pp. 731–733, Nov. 2004.
[37] T. Numata, T. Mizuno, T. Tezuka, J. Koga, and S. I. Takagi, “Control of threshold-voltage and short-channel effects in ultrathin strained-SOI CMOS devices,” IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1780–1786, Aug. 2005.
[38] R. Molaei Imen Abadi et al., “An Improved Si Tunnel Field Effect Transistor With a Buried Strained Si(1-x)Ge(x),” Microelectron. Eng., vol. 162, no. November, pp. 1480–1482, 2011.
