A 10-Bit Low Power SAR ADC with a New Control Logic Using Monotonic Capacitor-Switching
Subject Areas : Majlesi Journal of Telecommunication DevicesMorteza Rahimi 1 , Abbas Golmakani 2 , Mohammad Ali Heydari 3 , Mohammad Hossein Mesgarof 4
1 - Department of Electrical Engineering, Sadjad University of Technology, Mashhad, Iran
2 - Department of Electrical Engineering, Sadjad University of Technology, Mashhad, Iran
3 - Department of Electrical Engineering, Sadjad University of Technology, Mashhad, Iran
4 - Department of Electrical Engineering, Sadjad University of Technology, Mashhad, Iran
Keywords:
Abstract :
[1] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 0.92 mW 10-bit 50-MS/s SAR ADC in 0.13 m CMOS process,” in IEEE Symp. VLSI Circuits Dig, June 2009.
[2] D. Draxelmayr, “A 6 b 600 MHz 10 mW ADC array in digital 90 nm CMOS,” inIEEE ISSCC Dig. Tech. Papers, Feb 2004.
[3] M. D. Scott, B. E. Boser and K. S. J. Pister, “An Ultralow-Energy ADC for Smart Dust,” IEEE Journal of Solid-State Circuits, vol. 38, no. 7, July 2003.
[4] J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “A 0.5-v 1-µW Successive Approximation ADC,” IEEE Journal of Solid-State Circuits, vol. 38, no. 7 July 2003.
[5] N. Vermna and A. p. Chandrakasan, “A 25µW 100kS/s 12b ADC for Wireless Micro-Sensor Applications,” ISSCC Dig. Tech. Papers, pp. 222-223, Feb 2006.
[6] J. Craninckx and G. v. d. Plas, “A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS,” ISSCC Dig. Tech. Papers, Feb 2007.
[7] H. Ch. Hong and G. M. Lee, “A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC,” IEEE Journal of Solid-State Circuits, vol. 42, no. 10, Oct 2007.
[8] 10b 1MS/s Charge-Redistribution ADC,” ISSCC Dig. Tech. Papers, pp. 244-245, Feb 2008.
[9] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E.Klumperink, andB.Nauta,“A1.9 W 4.4 fJ/conversion-step 10b 1 MS/s chargeredistribution ADC,” inIEEE ISSCC Dig. Tech. Papers, Feb 2008.
[10] S. H. Cho, C. K. Lee, J. K. Kwon, and S. T. Ryu, “A 550-mW 10-b 40-MS/s SAR ADC with multistep addition-only digital error correction,”IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1–12, Aug 2011.
[11] Chun-Cheng Liu , Soon-Jyh Chang , Guan-Ying Huang , Ying-Zu Lin “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure” ,” IEEE Journal of Solid-State Circuits, APRIL 2010.
[12] Pascal Meinerzhagen,” Design of a 12-bit low-power SAR A/D Converter for a Neurochip” Master’s Thesis University of California 2008.
[13] S. W. M. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13- m CMOS,” inIEEE ISSCC Dig. Tech. Papers, Feb 2006.
[14] Jianhua Gan, B.S., M.S., Sc.D. “Non-Binary Capacitor Array Calibration for a High Performance Successive ApproximationAnalog-to-Digital Convert” dissertation the University of Texas at Austin 2003.